205 lines
6.1 KiB
C
205 lines
6.1 KiB
C
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _ADRENO_A5XX_H_
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#define _ADRENO_A5XX_H_
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#define A5XX_CP_CTXRECORD_MAGIC_REF 0x27C4BAFCUL
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/* Size of each CP preemption record */
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#define A5XX_CP_CTXRECORD_SIZE_IN_BYTES 0x100000
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/* Size of the preemption counter block (in bytes) */
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#define A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE (16 * 4)
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/**
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* struct a5xx_cp_preemption_record - CP context record for
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* preemption.
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* @magic: (00) Value at this offset must be equal to
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* A5XX_CP_CTXRECORD_MAGIC_REF.
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* @info: (04) Type of record. Written non-zero (usually) by CP.
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* we must set to zero for all ringbuffers.
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* @data: (08) DATA field in SET_RENDER_MODE or checkpoint packets.
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* Written by CP when switching out. Not used on switch-in.
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* we must initialize to zero.
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* @cntl: (12) RB_CNTL, saved and restored by CP.
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* @rptr: (16) RB_RPTR, saved and restored by CP.
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* @wptr: (20) RB_WPTR, saved and restored by CP.
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* @rptr_addr: (24) RB_RPTR_ADDR_LO|HI saved and restored.
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* rbase: (32) RB_BASE_LO|HI saved and restored.
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* counter: (40) Pointer to preemption counter
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*/
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struct a5xx_cp_preemption_record {
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uint32_t magic;
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uint32_t info;
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uint32_t data;
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uint32_t cntl;
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uint32_t rptr;
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uint32_t wptr;
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uint64_t rptr_addr;
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uint64_t rbase;
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uint64_t counter;
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};
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#define A5XX_CP_SMMU_INFO_MAGIC_REF 0x3618CDA3UL
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/**
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* struct a5xx_cp_smmu_info - CP preemption SMMU info.
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* @magic: (00) The value at this offset must be equal to
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* A5XX_CP_SMMU_INFO_MAGIC_REF.
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* @_pad4: (04) Reserved/padding
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* @ttbr0: (08) Base address of the page table for the
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* incoming context.
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* @context_idr: (16) Context Identification Register value.
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*/
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struct a5xx_cp_smmu_info {
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uint32_t magic;
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uint32_t _pad4;
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uint64_t ttbr0;
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uint32_t asid;
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uint32_t context_idr;
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};
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void a5xx_snapshot(struct adreno_device *adreno_dev,
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struct kgsl_snapshot *snapshot);
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unsigned int a5xx_num_registers(void);
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void a5xx_crashdump_init(struct adreno_device *adreno_dev);
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/* GPMU interrupt multiplexor */
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#define FW_INTR_INFO (0)
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#define LLM_ACK_ERR_INTR (1)
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#define ISENS_TRIM_ERR_INTR (2)
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#define ISENS_ERR_INTR (3)
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#define ISENS_IDLE_ERR_INTR (4)
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#define ISENS_PWR_ON_ERR_INTR (5)
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#define WDOG_EXPITED (31)
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#define VALID_GPMU_IRQ (\
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BIT(FW_INTR_INFO) | \
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BIT(LLM_ACK_ERR_INTR) | \
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BIT(ISENS_TRIM_ERR_INTR) | \
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BIT(ISENS_ERR_INTR) | \
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BIT(ISENS_IDLE_ERR_INTR) | \
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BIT(ISENS_PWR_ON_ERR_INTR) | \
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BIT(WDOG_EXPITED))
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/* A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL */
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#define STATE_OF_CHILD GENMASK(5, 4)
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#define STATE_OF_CHILD_01 BIT(4)
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#define STATE_OF_CHILD_11 (BIT(4) | BIT(5))
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#define IDLE_FULL_LM_SLEEP BIT(0)
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/* A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS */
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#define WAKEUP_ACK BIT(1)
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#define IDLE_FULL_ACK_SLEEP BIT(0)
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/* A5XX_GPMU_TEMP_SENSOR_CONFIG */
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#define GPMU_BCL_ENABLED BIT(4)
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#define GPMU_LLM_ENABLED BIT(9)
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#define GPMU_LMH_ENABLED BIT(8)
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#define GPMU_ISENSE_STATUS GENMASK(3, 0)
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#define GPMU_ISENSE_END_POINT_CAL_ERR BIT(0)
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/* A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 */
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#define AMP_SW_TRIM_START BIT(0)
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/* A5XX_GPU_CS_SENSOR_GENERAL_STATUS */
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#define SS_AMPTRIM_DONE BIT(11)
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#define CS_PWR_ON_STATUS BIT(10)
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/* A5XX_GPU_CS_AMP_CALIBRATION_STATUS*_* */
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#define AMP_OUT_OF_RANGE_ERR BIT(4)
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#define AMP_CHECK_TIMEOUT_ERR BIT(3)
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#define AMP_OFFSET_CHECK_MAX_ERR BIT(2)
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#define AMP_OFFSET_CHECK_MIN_ERR BIT(1)
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#define AMP_CALIBRATION_ERR (AMP_OFFSET_CHECK_MIN_ERR | \
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AMP_OFFSET_CHECK_MAX_ERR | AMP_OUT_OF_RANGE_ERR)
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#define AMP_CALIBRATION_RETRY_CNT 3
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#define AMP_CALIBRATION_TIMEOUT 6
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/* A5XX_GPMU_GPMU_PWR_THRESHOLD */
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#define PWR_THRESHOLD_VALID 0x80000000
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/* AGC */
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#define AGC_INIT_BASE A5XX_GPMU_DATA_RAM_BASE
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#define AGC_RVOUS_MAGIC (AGC_INIT_BASE + 0)
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#define AGC_KMD_GPMU_ADDR (AGC_INIT_BASE + 1)
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#define AGC_KMD_GPMU_BYTES (AGC_INIT_BASE + 2)
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#define AGC_GPMU_KMD_ADDR (AGC_INIT_BASE + 3)
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#define AGC_GPMU_KMD_BYTES (AGC_INIT_BASE + 4)
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#define AGC_INIT_MSG_MAGIC (AGC_INIT_BASE + 5)
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#define AGC_RESERVED (AGC_INIT_BASE + 6)
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#define AGC_MSG_BASE (AGC_INIT_BASE + 7)
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#define AGC_MSG_STATE (AGC_MSG_BASE + 0)
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#define AGC_MSG_COMMAND (AGC_MSG_BASE + 1)
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#define AGC_MSG_RETURN (AGC_MSG_BASE + 2)
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#define AGC_MSG_PAYLOAD_SIZE (AGC_MSG_BASE + 3)
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#define AGC_MSG_MAX_RETURN_SIZE (AGC_MSG_BASE + 4)
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#define AGC_MSG_PAYLOAD (AGC_MSG_BASE + 5)
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#define AGC_INIT_MSG_VALUE 0xBABEFACE
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#define AGC_POWER_CONFIG_PRODUCTION_ID 1
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#define AGC_LM_CONFIG (136/4)
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#define AGC_LM_CONFIG_ENABLE_GPMU_ADAPTIVE (1)
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#define AGC_LM_CONFIG_ENABLE_GPMU_LEGACY (2)
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#define AGC_LM_CONFIG_ENABLE_GPMU_LLM (3)
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#define AGC_LM_CONFIG_ENABLE_ISENSE (1 << 4)
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#define AGC_LM_CONFIG_ENABLE_DPM (2 << 4)
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#define AGC_LM_CONFIG_ENABLE_ERROR (3 << 4)
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#define AGC_THROTTLE_SEL_CRC (0 << 8)
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#define AGC_THROTTLE_SEL_DCS (1 << 8)
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#define AGC_LLM_ENABLED (1 << 16)
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#define AGC_GPU_VERSION_MASK GENMASK(18, 17)
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#define AGC_GPU_VERSION_SHIFT 17
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#define AGC_BCL_ENABLED (1 << 24)
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#define AGC_LEVEL_CONFIG (140/4)
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#define AGC_LEVEL_CONFIG_SENSOR_DISABLE GENMASK(15, 0)
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#define AGC_LEVEL_CONFIG_LMDISABLE GENMASK(31, 16)
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#define LM_DCVS_LIMIT 2
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/* FW file tages */
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#define GPMU_HEADER_ID 1
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#define GPMU_FIRMWARE_ID 2
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#define GPMU_SEQUENCE_ID 3
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#define GPMU_INST_RAM_SIZE 0xFFF
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#define HEADER_MAJOR 1
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#define HEADER_MINOR 2
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#define HEADER_DATE 3
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#define HEADER_TIME 4
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#define HEADER_SEQUENCE 5
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#define MAX_HEADER_SIZE 10
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#define LM_SEQUENCE_ID 1
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#define HWCG_SEQUENCE_ID 2
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#define MAX_SEQUENCE_ID 3
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/* LM defaults */
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#define LM_DEFAULT_LIMIT 6000
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#define A530_DEFAULT_LEAKAGE 0x004E001A
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static inline bool lm_on(struct adreno_device *adreno_dev)
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{
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return ADRENO_FEATURE(adreno_dev, ADRENO_LM) &&
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test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag);
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}
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#endif
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