371 lines
12 KiB
C
371 lines
12 KiB
C
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/io.h>
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#include "kgsl.h"
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#include "adreno.h"
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#include "kgsl_snapshot.h"
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#include "a3xx_reg.h"
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#include "adreno_snapshot.h"
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#include "adreno_a3xx.h"
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/*
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* Set of registers to dump for A3XX on snapshot.
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* Registers in pairs - first value is the start offset, second
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* is the stop offset (inclusive)
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*/
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static const unsigned int a3xx_registers[] = {
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0x0000, 0x0002, 0x0010, 0x0012, 0x0018, 0x0018, 0x0020, 0x0027,
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0x0029, 0x002b, 0x002e, 0x0033, 0x0040, 0x0042, 0x0050, 0x005c,
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0x0060, 0x006c, 0x0080, 0x0082, 0x0084, 0x0088, 0x0090, 0x00e5,
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0x00ea, 0x00ed, 0x0100, 0x0100, 0x0110, 0x0123, 0x01c0, 0x01c1,
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0x01c3, 0x01c5, 0x01c7, 0x01c7, 0x01d5, 0x01d9, 0x01dc, 0x01dd,
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0x01ea, 0x01ea, 0x01ee, 0x01f1, 0x01f5, 0x01f6, 0x01f8, 0x01f9,
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0x01fc, 0x01ff,
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0x0440, 0x0440, 0x0443, 0x0443, 0x0445, 0x0445, 0x044d, 0x044f,
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0x0452, 0x0452, 0x0454, 0x046f, 0x047c, 0x047c, 0x047f, 0x047f,
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0x0578, 0x057f, 0x0600, 0x0602, 0x0605, 0x0607, 0x060a, 0x060e,
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0x0612, 0x0614, 0x0c01, 0x0c02, 0x0c06, 0x0c1d, 0x0c3d, 0x0c3f,
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0x0c48, 0x0c4b, 0x0c80, 0x0c80, 0x0c88, 0x0c8b, 0x0ca0, 0x0cb7,
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0x0cc0, 0x0cc1, 0x0cc6, 0x0cc7, 0x0ce4, 0x0ce5,
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0x0e41, 0x0e45, 0x0e64, 0x0e65,
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0x0e80, 0x0e82, 0x0e84, 0x0e89, 0x0ea0, 0x0ea1, 0x0ea4, 0x0ea7,
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0x0ec4, 0x0ecb, 0x0ee0, 0x0ee0, 0x0f00, 0x0f01, 0x0f03, 0x0f09,
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0x2040, 0x2040, 0x2044, 0x2044, 0x2048, 0x204d, 0x2068, 0x2069,
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0x206c, 0x206d, 0x2070, 0x2070, 0x2072, 0x2072, 0x2074, 0x2075,
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0x2079, 0x207a, 0x20c0, 0x20d3, 0x20e4, 0x20ef, 0x2100, 0x2109,
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0x210c, 0x210c, 0x210e, 0x210e, 0x2110, 0x2111, 0x2114, 0x2115,
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0x21e4, 0x21e4, 0x21ea, 0x21ea, 0x21ec, 0x21ed, 0x21f0, 0x21f0,
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0x2240, 0x227e,
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0x2280, 0x228b, 0x22c0, 0x22c0, 0x22c4, 0x22ce, 0x22d0, 0x22d8,
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0x22df, 0x22e6, 0x22e8, 0x22e9, 0x22ec, 0x22ec, 0x22f0, 0x22f7,
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0x22ff, 0x22ff, 0x2340, 0x2343,
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0x2440, 0x2440, 0x2444, 0x2444, 0x2448, 0x244d,
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0x2468, 0x2469, 0x246c, 0x246d, 0x2470, 0x2470, 0x2472, 0x2472,
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0x2474, 0x2475, 0x2479, 0x247a, 0x24c0, 0x24d3, 0x24e4, 0x24ef,
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0x2500, 0x2509, 0x250c, 0x250c, 0x250e, 0x250e, 0x2510, 0x2511,
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0x2514, 0x2515, 0x25e4, 0x25e4, 0x25ea, 0x25ea, 0x25ec, 0x25ed,
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0x25f0, 0x25f0,
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0x2640, 0x267e, 0x2680, 0x268b, 0x26c0, 0x26c0, 0x26c4, 0x26ce,
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0x26d0, 0x26d8, 0x26df, 0x26e6, 0x26e8, 0x26e9, 0x26ec, 0x26ec,
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0x26f0, 0x26f7, 0x26ff, 0x26ff, 0x2740, 0x2743,
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0x300C, 0x300E, 0x301C, 0x301D,
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0x302A, 0x302A, 0x302C, 0x302D, 0x3030, 0x3031, 0x3034, 0x3036,
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0x303C, 0x303C, 0x305E, 0x305F,
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};
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/* Removed the following HLSQ register ranges from being read during
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* fault tolerance since reading the registers may cause the device to hang:
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*/
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static const unsigned int a3xx_hlsq_registers[] = {
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0x0e00, 0x0e05, 0x0e0c, 0x0e0c, 0x0e22, 0x0e23,
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0x2200, 0x2212, 0x2214, 0x2217, 0x221a, 0x221a,
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0x2600, 0x2612, 0x2614, 0x2617, 0x261a, 0x261a,
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};
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/* The set of additional registers to be dumped for A330 */
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static const unsigned int a330_registers[] = {
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0x1d0, 0x1d0, 0x1d4, 0x1d4, 0x453, 0x453,
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};
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/* Shader memory size in words */
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#define SHADER_MEMORY_SIZE 0x4000
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/**
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* _rbbm_debug_bus_read - Helper function to read data from the RBBM
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* debug bus.
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* @device - GPU device to read/write registers
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* @block_id - Debug bus block to read from
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* @index - Index in the debug bus block to read
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* @ret - Value of the register read
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*/
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static void _rbbm_debug_bus_read(struct kgsl_device *device,
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unsigned int block_id, unsigned int index, unsigned int *val)
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{
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unsigned int block = (block_id << 8) | 1 << 16;
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kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_CTL, block | index);
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kgsl_regread(device, A3XX_RBBM_DEBUG_BUS_DATA_STATUS, val);
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}
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/**
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* a3xx_snapshot_shader_memory - Helper function to dump the GPU shader
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* memory to the snapshot buffer.
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* @device: GPU device whose shader memory is to be dumped
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* @buf: Pointer to binary snapshot data blob being made
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* @remain: Number of remaining bytes in the snapshot blob
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* @priv: Unused parameter
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*
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*/
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static size_t a3xx_snapshot_shader_memory(struct kgsl_device *device,
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u8 *buf, size_t remain, void *priv)
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{
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struct kgsl_snapshot_debug *header = (struct kgsl_snapshot_debug *)buf;
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unsigned int i;
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unsigned int *data = (unsigned int *)(buf + sizeof(*header));
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unsigned int shader_read_len = SHADER_MEMORY_SIZE;
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if (shader_read_len > (device->shader_mem_len >> 2))
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shader_read_len = (device->shader_mem_len >> 2);
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if (remain < DEBUG_SECTION_SZ(shader_read_len)) {
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SNAPSHOT_ERR_NOMEM(device, "SHADER MEMORY");
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return 0;
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}
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header->type = SNAPSHOT_DEBUG_SHADER_MEMORY;
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header->size = shader_read_len;
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/* Map shader memory to kernel, for dumping */
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if (device->shader_mem_virt == NULL)
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device->shader_mem_virt = devm_ioremap(device->dev,
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device->shader_mem_phys,
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device->shader_mem_len);
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if (device->shader_mem_virt == NULL) {
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KGSL_DRV_ERR(device,
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"Unable to map shader memory region\n");
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return 0;
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}
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/* Now, dump shader memory to snapshot */
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for (i = 0; i < shader_read_len; i++)
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adreno_shadermem_regread(device, i, &data[i]);
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return DEBUG_SECTION_SZ(shader_read_len);
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}
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static size_t a3xx_snapshot_debugbus_block(struct kgsl_device *device,
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u8 *buf, size_t remain, void *priv)
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{
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struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
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struct kgsl_snapshot_debugbus *header
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= (struct kgsl_snapshot_debugbus *)buf;
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struct adreno_debugbus_block *block = priv;
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int i;
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unsigned int *data = (unsigned int *)(buf + sizeof(*header));
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unsigned int dwords;
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size_t size;
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/*
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* For A305 and A320 all debug bus regions are the same size (0x40). For
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* A330, they can be different sizes - most are still 0x40, but some
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* like CP are larger
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*/
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dwords = (adreno_is_a330(adreno_dev) ||
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adreno_is_a305b(adreno_dev)) ?
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block->dwords : 0x40;
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size = (dwords * sizeof(unsigned int)) + sizeof(*header);
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if (remain < size) {
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SNAPSHOT_ERR_NOMEM(device, "DEBUGBUS");
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return 0;
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}
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header->id = block->block_id;
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header->count = dwords;
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for (i = 0; i < dwords; i++)
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_rbbm_debug_bus_read(device, block->block_id, i, &data[i]);
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return size;
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}
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static struct adreno_debugbus_block debugbus_blocks[] = {
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{ RBBM_BLOCK_ID_CP, 0x52, },
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{ RBBM_BLOCK_ID_RBBM, 0x40, },
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{ RBBM_BLOCK_ID_VBIF, 0x40, },
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{ RBBM_BLOCK_ID_HLSQ, 0x40, },
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{ RBBM_BLOCK_ID_UCHE, 0x40, },
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{ RBBM_BLOCK_ID_PC, 0x40, },
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{ RBBM_BLOCK_ID_VFD, 0x40, },
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{ RBBM_BLOCK_ID_VPC, 0x40, },
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{ RBBM_BLOCK_ID_TSE, 0x40, },
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{ RBBM_BLOCK_ID_RAS, 0x40, },
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{ RBBM_BLOCK_ID_VSC, 0x40, },
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{ RBBM_BLOCK_ID_SP_0, 0x40, },
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{ RBBM_BLOCK_ID_SP_1, 0x40, },
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{ RBBM_BLOCK_ID_SP_2, 0x40, },
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{ RBBM_BLOCK_ID_SP_3, 0x40, },
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{ RBBM_BLOCK_ID_TPL1_0, 0x40, },
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{ RBBM_BLOCK_ID_TPL1_1, 0x40, },
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{ RBBM_BLOCK_ID_TPL1_2, 0x40, },
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{ RBBM_BLOCK_ID_TPL1_3, 0x40, },
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{ RBBM_BLOCK_ID_RB_0, 0x40, },
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{ RBBM_BLOCK_ID_RB_1, 0x40, },
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{ RBBM_BLOCK_ID_RB_2, 0x40, },
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{ RBBM_BLOCK_ID_RB_3, 0x40, },
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{ RBBM_BLOCK_ID_MARB_0, 0x40, },
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{ RBBM_BLOCK_ID_MARB_1, 0x40, },
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{ RBBM_BLOCK_ID_MARB_2, 0x40, },
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{ RBBM_BLOCK_ID_MARB_3, 0x40, },
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};
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static void a3xx_snapshot_debugbus(struct kgsl_device *device,
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struct kgsl_snapshot *snapshot)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(debugbus_blocks); i++) {
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kgsl_snapshot_add_section(device,
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KGSL_SNAPSHOT_SECTION_DEBUGBUS, snapshot,
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a3xx_snapshot_debugbus_block,
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(void *) &debugbus_blocks[i]);
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}
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}
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static void _snapshot_hlsq_regs(struct kgsl_device *device,
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struct kgsl_snapshot *snapshot)
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{
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struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
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/*
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* Trying to read HLSQ registers when the HLSQ block is busy
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* will cause the device to hang. The RBBM_DEBUG_BUS has information
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* that will tell us if the HLSQ block is busy or not. Read values
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* from the debug bus to ensure the HLSQ block is not busy (this
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* is hardware dependent). If the HLSQ block is busy do not
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* dump the registers, otherwise dump the HLSQ registers.
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*/
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if (adreno_is_a330(adreno_dev)) {
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/*
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* stall_ctxt_full status bit: RBBM_BLOCK_ID_HLSQ index 49 [27]
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*
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* if (!stall_context_full)
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* then dump HLSQ registers
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*/
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unsigned int stall_context_full = 0;
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_rbbm_debug_bus_read(device, RBBM_BLOCK_ID_HLSQ, 49,
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&stall_context_full);
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stall_context_full &= 0x08000000;
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if (stall_context_full)
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return;
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} else {
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/*
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* tpif status bits: RBBM_BLOCK_ID_HLSQ index 4 [4:0]
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* spif status bits: RBBM_BLOCK_ID_HLSQ index 7 [5:0]
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*
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* if ((tpif == 0, 1, 28) && (spif == 0, 1, 10))
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* then dump HLSQ registers
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*/
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unsigned int next_pif = 0;
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/* check tpif */
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_rbbm_debug_bus_read(device, RBBM_BLOCK_ID_HLSQ, 4, &next_pif);
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next_pif &= 0x1f;
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if (next_pif != 0 && next_pif != 1 && next_pif != 28)
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return;
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/* check spif */
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_rbbm_debug_bus_read(device, RBBM_BLOCK_ID_HLSQ, 7, &next_pif);
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next_pif &= 0x3f;
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if (next_pif != 0 && next_pif != 1 && next_pif != 10)
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return;
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}
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SNAPSHOT_REGISTERS(device, snapshot, a3xx_hlsq_registers);
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}
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/*
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* a3xx_snapshot() - A3XX GPU snapshot function
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* @adreno_dev: Device being snapshotted
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* @snapshot: Snapshot meta data
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* @remain: Amount of space left in snapshot memory
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*
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* This is where all of the A3XX specific bits and pieces are grabbed
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* into the snapshot memory
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*/
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void a3xx_snapshot(struct adreno_device *adreno_dev,
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struct kgsl_snapshot *snapshot)
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{
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struct kgsl_device *device = &adreno_dev->dev;
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struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
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struct adreno_snapshot_data *snap_data = gpudev->snapshot_data;
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unsigned int reg;
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/* Disable Clock gating temporarily for the debug bus to work */
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adreno_writereg(adreno_dev, ADRENO_REG_RBBM_CLOCK_CTL, 0x00);
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SNAPSHOT_REGISTERS(device, snapshot, a3xx_registers);
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_snapshot_hlsq_regs(device, snapshot);
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if (adreno_is_a330(adreno_dev) || adreno_is_a305b(adreno_dev))
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SNAPSHOT_REGISTERS(device, snapshot, a330_registers);
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kgsl_snapshot_indexed_registers(device, snapshot,
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A3XX_CP_STATE_DEBUG_INDEX, A3XX_CP_STATE_DEBUG_DATA,
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0x0, snap_data->sect_sizes->cp_pfp);
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/* CP_ME indexed registers */
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kgsl_snapshot_indexed_registers(device, snapshot,
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A3XX_CP_ME_CNTL, A3XX_CP_ME_STATUS, 64, 44);
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/* VPC memory */
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kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG,
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snapshot, adreno_snapshot_vpc_memory,
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&snap_data->sect_sizes->vpc_mem);
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/* CP MEQ */
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kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG, snapshot,
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adreno_snapshot_cp_meq, &snap_data->sect_sizes->cp_meq);
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/* Shader working/shadow memory */
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kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG,
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snapshot, a3xx_snapshot_shader_memory,
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&snap_data->sect_sizes->shader_mem);
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/* CP PFP and PM4 */
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/*
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* Reading the microcode while the CP is running will
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* basically move the CP instruction pointer to
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* whatever address we read. Big badaboom ensues. Stop the CP
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* (if it isn't already stopped) to ensure that we are safe.
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* We do this here and not earlier to avoid corrupting the RBBM
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* status and CP registers - by the time we get here we don't
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* care about the contents of the CP anymore.
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*/
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adreno_readreg(adreno_dev, ADRENO_REG_CP_ME_CNTL, ®);
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reg |= (1 << 27) | (1 << 28);
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adreno_writereg(adreno_dev, ADRENO_REG_CP_ME_CNTL, reg);
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kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG,
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snapshot, adreno_snapshot_cp_pfp_ram, NULL);
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kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG,
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snapshot, adreno_snapshot_cp_pm4_ram, NULL);
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/* CP ROQ */
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kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG,
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snapshot, adreno_snapshot_cp_roq, &snap_data->sect_sizes->roq);
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if (snap_data->sect_sizes->cp_merciu) {
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kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_DEBUG,
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snapshot, adreno_snapshot_cp_merciu,
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&snap_data->sect_sizes->cp_merciu);
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}
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a3xx_snapshot_debugbus(device, snapshot);
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}
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