567 lines
15 KiB
C
567 lines
15 KiB
C
/*
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* Cryptographic API.
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*
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* Support for VIA PadLock hardware crypto engine.
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*
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* Copyright (c) 2004 Michal Ludvig <michal@logix.cz>
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*
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*/
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#include <crypto/algapi.h>
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#include <crypto/aes.h>
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#include <crypto/padlock.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/percpu.h>
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#include <linux/smp.h>
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#include <linux/slab.h>
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#include <asm/cpu_device_id.h>
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#include <asm/byteorder.h>
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#include <asm/processor.h>
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#include <asm/i387.h>
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/*
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* Number of data blocks actually fetched for each xcrypt insn.
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* Processors with prefetch errata will fetch extra blocks.
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*/
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static unsigned int ecb_fetch_blocks = 2;
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#define MAX_ECB_FETCH_BLOCKS (8)
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#define ecb_fetch_bytes (ecb_fetch_blocks * AES_BLOCK_SIZE)
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static unsigned int cbc_fetch_blocks = 1;
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#define MAX_CBC_FETCH_BLOCKS (4)
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#define cbc_fetch_bytes (cbc_fetch_blocks * AES_BLOCK_SIZE)
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/* Control word. */
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struct cword {
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unsigned int __attribute__ ((__packed__))
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rounds:4,
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algo:3,
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keygen:1,
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interm:1,
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encdec:1,
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ksize:2;
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} __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
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/* Whenever making any changes to the following
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* structure *make sure* you keep E, d_data
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* and cword aligned on 16 Bytes boundaries and
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* the Hardware can access 16 * 16 bytes of E and d_data
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* (only the first 15 * 16 bytes matter but the HW reads
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* more).
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*/
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struct aes_ctx {
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u32 E[AES_MAX_KEYLENGTH_U32]
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__attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
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u32 d_data[AES_MAX_KEYLENGTH_U32]
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__attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
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struct {
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struct cword encrypt;
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struct cword decrypt;
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} cword;
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u32 *D;
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};
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static DEFINE_PER_CPU(struct cword *, paes_last_cword);
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/* Tells whether the ACE is capable to generate
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the extended key for a given key_len. */
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static inline int
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aes_hw_extkey_available(uint8_t key_len)
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{
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/* TODO: We should check the actual CPU model/stepping
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as it's possible that the capability will be
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added in the next CPU revisions. */
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if (key_len == 16)
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return 1;
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return 0;
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}
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static inline struct aes_ctx *aes_ctx_common(void *ctx)
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{
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unsigned long addr = (unsigned long)ctx;
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unsigned long align = PADLOCK_ALIGNMENT;
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if (align <= crypto_tfm_ctx_alignment())
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align = 1;
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return (struct aes_ctx *)ALIGN(addr, align);
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}
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static inline struct aes_ctx *aes_ctx(struct crypto_tfm *tfm)
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{
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return aes_ctx_common(crypto_tfm_ctx(tfm));
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}
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static inline struct aes_ctx *blk_aes_ctx(struct crypto_blkcipher *tfm)
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{
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return aes_ctx_common(crypto_blkcipher_ctx(tfm));
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}
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static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
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unsigned int key_len)
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{
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struct aes_ctx *ctx = aes_ctx(tfm);
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const __le32 *key = (const __le32 *)in_key;
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u32 *flags = &tfm->crt_flags;
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struct crypto_aes_ctx gen_aes;
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int cpu;
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if (key_len % 8) {
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*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
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return -EINVAL;
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}
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/*
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* If the hardware is capable of generating the extended key
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* itself we must supply the plain key for both encryption
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* and decryption.
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*/
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ctx->D = ctx->E;
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ctx->E[0] = le32_to_cpu(key[0]);
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ctx->E[1] = le32_to_cpu(key[1]);
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ctx->E[2] = le32_to_cpu(key[2]);
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ctx->E[3] = le32_to_cpu(key[3]);
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/* Prepare control words. */
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memset(&ctx->cword, 0, sizeof(ctx->cword));
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ctx->cword.decrypt.encdec = 1;
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ctx->cword.encrypt.rounds = 10 + (key_len - 16) / 4;
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ctx->cword.decrypt.rounds = ctx->cword.encrypt.rounds;
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ctx->cword.encrypt.ksize = (key_len - 16) / 8;
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ctx->cword.decrypt.ksize = ctx->cword.encrypt.ksize;
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/* Don't generate extended keys if the hardware can do it. */
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if (aes_hw_extkey_available(key_len))
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goto ok;
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ctx->D = ctx->d_data;
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ctx->cword.encrypt.keygen = 1;
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ctx->cword.decrypt.keygen = 1;
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if (crypto_aes_expand_key(&gen_aes, in_key, key_len)) {
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*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
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return -EINVAL;
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}
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memcpy(ctx->E, gen_aes.key_enc, AES_MAX_KEYLENGTH);
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memcpy(ctx->D, gen_aes.key_dec, AES_MAX_KEYLENGTH);
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ok:
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for_each_online_cpu(cpu)
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if (&ctx->cword.encrypt == per_cpu(paes_last_cword, cpu) ||
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&ctx->cword.decrypt == per_cpu(paes_last_cword, cpu))
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per_cpu(paes_last_cword, cpu) = NULL;
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return 0;
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}
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/* ====== Encryption/decryption routines ====== */
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/* These are the real call to PadLock. */
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static inline void padlock_reset_key(struct cword *cword)
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{
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int cpu = raw_smp_processor_id();
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if (cword != per_cpu(paes_last_cword, cpu))
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#ifndef CONFIG_X86_64
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asm volatile ("pushfl; popfl");
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#else
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asm volatile ("pushfq; popfq");
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#endif
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}
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static inline void padlock_store_cword(struct cword *cword)
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{
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per_cpu(paes_last_cword, raw_smp_processor_id()) = cword;
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}
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/*
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* While the padlock instructions don't use FP/SSE registers, they
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* generate a spurious DNA fault when cr0.ts is '1'. These instructions
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* should be used only inside the irq_ts_save/restore() context
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*/
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static inline void rep_xcrypt_ecb(const u8 *input, u8 *output, void *key,
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struct cword *control_word, int count)
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{
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asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */
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: "+S"(input), "+D"(output)
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: "d"(control_word), "b"(key), "c"(count));
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}
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static inline u8 *rep_xcrypt_cbc(const u8 *input, u8 *output, void *key,
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u8 *iv, struct cword *control_word, int count)
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{
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asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */
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: "+S" (input), "+D" (output), "+a" (iv)
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: "d" (control_word), "b" (key), "c" (count));
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return iv;
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}
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static void ecb_crypt_copy(const u8 *in, u8 *out, u32 *key,
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struct cword *cword, int count)
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{
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/*
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* Padlock prefetches extra data so we must provide mapped input buffers.
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* Assume there are at least 16 bytes of stack already in use.
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*/
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u8 buf[AES_BLOCK_SIZE * (MAX_ECB_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];
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u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
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memcpy(tmp, in, count * AES_BLOCK_SIZE);
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rep_xcrypt_ecb(tmp, out, key, cword, count);
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}
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static u8 *cbc_crypt_copy(const u8 *in, u8 *out, u32 *key,
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u8 *iv, struct cword *cword, int count)
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{
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/*
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* Padlock prefetches extra data so we must provide mapped input buffers.
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* Assume there are at least 16 bytes of stack already in use.
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*/
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u8 buf[AES_BLOCK_SIZE * (MAX_CBC_FETCH_BLOCKS - 1) + PADLOCK_ALIGNMENT - 1];
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u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
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memcpy(tmp, in, count * AES_BLOCK_SIZE);
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return rep_xcrypt_cbc(tmp, out, key, iv, cword, count);
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}
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static inline void ecb_crypt(const u8 *in, u8 *out, u32 *key,
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struct cword *cword, int count)
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{
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/* Padlock in ECB mode fetches at least ecb_fetch_bytes of data.
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* We could avoid some copying here but it's probably not worth it.
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*/
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if (unlikely(((unsigned long)in & ~PAGE_MASK) + ecb_fetch_bytes > PAGE_SIZE)) {
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ecb_crypt_copy(in, out, key, cword, count);
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return;
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}
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rep_xcrypt_ecb(in, out, key, cword, count);
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}
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static inline u8 *cbc_crypt(const u8 *in, u8 *out, u32 *key,
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u8 *iv, struct cword *cword, int count)
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{
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/* Padlock in CBC mode fetches at least cbc_fetch_bytes of data. */
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if (unlikely(((unsigned long)in & ~PAGE_MASK) + cbc_fetch_bytes > PAGE_SIZE))
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return cbc_crypt_copy(in, out, key, iv, cword, count);
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return rep_xcrypt_cbc(in, out, key, iv, cword, count);
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}
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static inline void padlock_xcrypt_ecb(const u8 *input, u8 *output, void *key,
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void *control_word, u32 count)
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{
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u32 initial = count & (ecb_fetch_blocks - 1);
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if (count < ecb_fetch_blocks) {
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ecb_crypt(input, output, key, control_word, count);
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return;
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}
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if (initial)
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asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */
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: "+S"(input), "+D"(output)
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: "d"(control_word), "b"(key), "c"(initial));
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asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */
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: "+S"(input), "+D"(output)
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: "d"(control_word), "b"(key), "c"(count - initial));
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}
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static inline u8 *padlock_xcrypt_cbc(const u8 *input, u8 *output, void *key,
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u8 *iv, void *control_word, u32 count)
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{
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u32 initial = count & (cbc_fetch_blocks - 1);
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if (count < cbc_fetch_blocks)
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return cbc_crypt(input, output, key, iv, control_word, count);
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if (initial)
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asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */
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: "+S" (input), "+D" (output), "+a" (iv)
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: "d" (control_word), "b" (key), "c" (initial));
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asm volatile (".byte 0xf3,0x0f,0xa7,0xd0" /* rep xcryptcbc */
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: "+S" (input), "+D" (output), "+a" (iv)
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: "d" (control_word), "b" (key), "c" (count-initial));
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return iv;
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}
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static void aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
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{
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struct aes_ctx *ctx = aes_ctx(tfm);
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int ts_state;
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padlock_reset_key(&ctx->cword.encrypt);
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ts_state = irq_ts_save();
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ecb_crypt(in, out, ctx->E, &ctx->cword.encrypt, 1);
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irq_ts_restore(ts_state);
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padlock_store_cword(&ctx->cword.encrypt);
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}
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static void aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
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{
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struct aes_ctx *ctx = aes_ctx(tfm);
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int ts_state;
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padlock_reset_key(&ctx->cword.encrypt);
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ts_state = irq_ts_save();
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ecb_crypt(in, out, ctx->D, &ctx->cword.decrypt, 1);
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irq_ts_restore(ts_state);
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padlock_store_cword(&ctx->cword.encrypt);
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}
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static struct crypto_alg aes_alg = {
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.cra_name = "aes",
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.cra_driver_name = "aes-padlock",
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.cra_priority = PADLOCK_CRA_PRIORITY,
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.cra_flags = CRYPTO_ALG_TYPE_CIPHER,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct aes_ctx),
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.cra_alignmask = PADLOCK_ALIGNMENT - 1,
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.cra_module = THIS_MODULE,
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.cra_u = {
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.cipher = {
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.cia_min_keysize = AES_MIN_KEY_SIZE,
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.cia_max_keysize = AES_MAX_KEY_SIZE,
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.cia_setkey = aes_set_key,
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.cia_encrypt = aes_encrypt,
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.cia_decrypt = aes_decrypt,
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}
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}
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};
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static int ecb_aes_encrypt(struct blkcipher_desc *desc,
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struct scatterlist *dst, struct scatterlist *src,
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unsigned int nbytes)
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{
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struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
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struct blkcipher_walk walk;
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int err;
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int ts_state;
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padlock_reset_key(&ctx->cword.encrypt);
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blkcipher_walk_init(&walk, dst, src, nbytes);
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err = blkcipher_walk_virt(desc, &walk);
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ts_state = irq_ts_save();
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while ((nbytes = walk.nbytes)) {
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padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
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ctx->E, &ctx->cword.encrypt,
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nbytes / AES_BLOCK_SIZE);
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nbytes &= AES_BLOCK_SIZE - 1;
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err = blkcipher_walk_done(desc, &walk, nbytes);
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}
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irq_ts_restore(ts_state);
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padlock_store_cword(&ctx->cword.encrypt);
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return err;
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}
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static int ecb_aes_decrypt(struct blkcipher_desc *desc,
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struct scatterlist *dst, struct scatterlist *src,
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unsigned int nbytes)
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{
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struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
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struct blkcipher_walk walk;
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int err;
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int ts_state;
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padlock_reset_key(&ctx->cword.decrypt);
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blkcipher_walk_init(&walk, dst, src, nbytes);
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err = blkcipher_walk_virt(desc, &walk);
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ts_state = irq_ts_save();
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while ((nbytes = walk.nbytes)) {
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padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
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ctx->D, &ctx->cword.decrypt,
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nbytes / AES_BLOCK_SIZE);
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nbytes &= AES_BLOCK_SIZE - 1;
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err = blkcipher_walk_done(desc, &walk, nbytes);
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}
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irq_ts_restore(ts_state);
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padlock_store_cword(&ctx->cword.encrypt);
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return err;
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}
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static struct crypto_alg ecb_aes_alg = {
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.cra_name = "ecb(aes)",
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.cra_driver_name = "ecb-aes-padlock",
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.cra_priority = PADLOCK_COMPOSITE_PRIORITY,
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.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct aes_ctx),
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.cra_alignmask = PADLOCK_ALIGNMENT - 1,
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.cra_type = &crypto_blkcipher_type,
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.cra_module = THIS_MODULE,
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.cra_u = {
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.blkcipher = {
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.min_keysize = AES_MIN_KEY_SIZE,
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.max_keysize = AES_MAX_KEY_SIZE,
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.setkey = aes_set_key,
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.encrypt = ecb_aes_encrypt,
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.decrypt = ecb_aes_decrypt,
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}
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}
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};
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static int cbc_aes_encrypt(struct blkcipher_desc *desc,
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struct scatterlist *dst, struct scatterlist *src,
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unsigned int nbytes)
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{
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struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
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struct blkcipher_walk walk;
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int err;
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int ts_state;
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padlock_reset_key(&ctx->cword.encrypt);
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blkcipher_walk_init(&walk, dst, src, nbytes);
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err = blkcipher_walk_virt(desc, &walk);
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ts_state = irq_ts_save();
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while ((nbytes = walk.nbytes)) {
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u8 *iv = padlock_xcrypt_cbc(walk.src.virt.addr,
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walk.dst.virt.addr, ctx->E,
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walk.iv, &ctx->cword.encrypt,
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nbytes / AES_BLOCK_SIZE);
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memcpy(walk.iv, iv, AES_BLOCK_SIZE);
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nbytes &= AES_BLOCK_SIZE - 1;
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err = blkcipher_walk_done(desc, &walk, nbytes);
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}
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irq_ts_restore(ts_state);
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padlock_store_cword(&ctx->cword.decrypt);
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return err;
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}
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static int cbc_aes_decrypt(struct blkcipher_desc *desc,
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struct scatterlist *dst, struct scatterlist *src,
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unsigned int nbytes)
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{
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struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
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struct blkcipher_walk walk;
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int err;
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int ts_state;
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padlock_reset_key(&ctx->cword.encrypt);
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blkcipher_walk_init(&walk, dst, src, nbytes);
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err = blkcipher_walk_virt(desc, &walk);
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ts_state = irq_ts_save();
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while ((nbytes = walk.nbytes)) {
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padlock_xcrypt_cbc(walk.src.virt.addr, walk.dst.virt.addr,
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ctx->D, walk.iv, &ctx->cword.decrypt,
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nbytes / AES_BLOCK_SIZE);
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nbytes &= AES_BLOCK_SIZE - 1;
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err = blkcipher_walk_done(desc, &walk, nbytes);
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}
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irq_ts_restore(ts_state);
|
|
|
|
padlock_store_cword(&ctx->cword.encrypt);
|
|
|
|
return err;
|
|
}
|
|
|
|
static struct crypto_alg cbc_aes_alg = {
|
|
.cra_name = "cbc(aes)",
|
|
.cra_driver_name = "cbc-aes-padlock",
|
|
.cra_priority = PADLOCK_COMPOSITE_PRIORITY,
|
|
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct aes_ctx),
|
|
.cra_alignmask = PADLOCK_ALIGNMENT - 1,
|
|
.cra_type = &crypto_blkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_u = {
|
|
.blkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.setkey = aes_set_key,
|
|
.encrypt = cbc_aes_encrypt,
|
|
.decrypt = cbc_aes_decrypt,
|
|
}
|
|
}
|
|
};
|
|
|
|
static struct x86_cpu_id padlock_cpu_id[] = {
|
|
X86_FEATURE_MATCH(X86_FEATURE_XCRYPT),
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(x86cpu, padlock_cpu_id);
|
|
|
|
static int __init padlock_init(void)
|
|
{
|
|
int ret;
|
|
struct cpuinfo_x86 *c = &cpu_data(0);
|
|
|
|
if (!x86_match_cpu(padlock_cpu_id))
|
|
return -ENODEV;
|
|
|
|
if (!cpu_has_xcrypt_enabled) {
|
|
printk(KERN_NOTICE PFX "VIA PadLock detected, but not enabled. Hmm, strange...\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if ((ret = crypto_register_alg(&aes_alg)))
|
|
goto aes_err;
|
|
|
|
if ((ret = crypto_register_alg(&ecb_aes_alg)))
|
|
goto ecb_aes_err;
|
|
|
|
if ((ret = crypto_register_alg(&cbc_aes_alg)))
|
|
goto cbc_aes_err;
|
|
|
|
printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n");
|
|
|
|
if (c->x86 == 6 && c->x86_model == 15 && c->x86_mask == 2) {
|
|
ecb_fetch_blocks = MAX_ECB_FETCH_BLOCKS;
|
|
cbc_fetch_blocks = MAX_CBC_FETCH_BLOCKS;
|
|
printk(KERN_NOTICE PFX "VIA Nano stepping 2 detected: enabling workaround.\n");
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
|
|
cbc_aes_err:
|
|
crypto_unregister_alg(&ecb_aes_alg);
|
|
ecb_aes_err:
|
|
crypto_unregister_alg(&aes_alg);
|
|
aes_err:
|
|
printk(KERN_ERR PFX "VIA PadLock AES initialization failed.\n");
|
|
goto out;
|
|
}
|
|
|
|
static void __exit padlock_fini(void)
|
|
{
|
|
crypto_unregister_alg(&cbc_aes_alg);
|
|
crypto_unregister_alg(&ecb_aes_alg);
|
|
crypto_unregister_alg(&aes_alg);
|
|
}
|
|
|
|
module_init(padlock_init);
|
|
module_exit(padlock_fini);
|
|
|
|
MODULE_DESCRIPTION("VIA PadLock AES algorithm support");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Michal Ludvig");
|
|
|
|
MODULE_ALIAS_CRYPTO("aes");
|