526 lines
17 KiB
C
526 lines
17 KiB
C
/*
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* Clock definitions for u8500 platform.
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*
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* Copyright (C) 2012 ST-Ericsson SA
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* Author: Ulf Hansson <ulf.hansson@linaro.org>
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/mfd/dbx500-prcmu.h>
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#include <linux/platform_data/clk-ux500.h>
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#include "clk.h"
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void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
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u32 clkrst5_base, u32 clkrst6_base)
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{
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struct prcmu_fw_version *fw_version;
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const char *sgaclk_parent = NULL;
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struct clk *clk;
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/* Clock sources */
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clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
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CLK_IS_ROOT|CLK_IGNORE_UNUSED);
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clk_register_clkdev(clk, "soc0_pll", NULL);
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clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
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CLK_IS_ROOT|CLK_IGNORE_UNUSED);
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clk_register_clkdev(clk, "soc1_pll", NULL);
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clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
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CLK_IS_ROOT|CLK_IGNORE_UNUSED);
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clk_register_clkdev(clk, "ddr_pll", NULL);
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/* FIXME: Add sys, ulp and int clocks here. */
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clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
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CLK_IS_ROOT|CLK_IGNORE_UNUSED,
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32768);
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clk_register_clkdev(clk, "clk32k", NULL);
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clk_register_clkdev(clk, "apb_pclk", "rtc-pl031");
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/* PRCMU clocks */
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fw_version = prcmu_get_fw_version();
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if (fw_version != NULL) {
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switch (fw_version->project) {
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case PRCMU_FW_PROJECT_U8500_C2:
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case PRCMU_FW_PROJECT_U8520:
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case PRCMU_FW_PROJECT_U8420:
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sgaclk_parent = "soc0_pll";
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break;
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default:
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break;
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}
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}
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if (sgaclk_parent)
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clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
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PRCMU_SGACLK, 0);
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else
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clk = clk_reg_prcmu_gate("sgclk", NULL,
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PRCMU_SGACLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "mali");
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clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "UART");
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clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "MSP02");
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clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "MSP1");
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clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "I2C");
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clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "slim");
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clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "PERIPH1");
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clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "PERIPH2");
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clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "PERIPH3");
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clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "PERIPH5");
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clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "PERIPH6");
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clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "PERIPH7");
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clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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clk_register_clkdev(clk, NULL, "lcd");
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clk_register_clkdev(clk, "lcd", "mcde");
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clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "bml");
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clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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clk_register_clkdev(clk, NULL, "hdmi");
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clk_register_clkdev(clk, "hdmi", "mcde");
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clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "apeat");
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clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
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CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "apetrace");
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clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "mcde");
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clk_register_clkdev(clk, "mcde", "mcde");
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clk_register_clkdev(clk, "dsisys", "dsilink.0");
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clk_register_clkdev(clk, "dsisys", "dsilink.1");
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clk_register_clkdev(clk, "dsisys", "dsilink.2");
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clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
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CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "ipi2");
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clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
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CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "dsialt");
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clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "dma40.0");
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clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "b2r2");
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clk_register_clkdev(clk, NULL, "b2r2_core");
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clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
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clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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clk_register_clkdev(clk, NULL, "tv");
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clk_register_clkdev(clk, "tv", "mcde");
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clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "SSP");
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clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "rngclk");
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clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "uicc");
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clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
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clk_register_clkdev(clk, NULL, "mtu0");
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clk_register_clkdev(clk, NULL, "mtu1");
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clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
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100000000,
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CLK_IS_ROOT|CLK_SET_RATE_GATE);
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clk_register_clkdev(clk, NULL, "sdmmc");
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clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
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PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
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clk_register_clkdev(clk, "dsihs2", "mcde");
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clk_register_clkdev(clk, "dsihs2", "dsilink.2");
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clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
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PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
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clk_register_clkdev(clk, "dsihs0", "mcde");
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clk_register_clkdev(clk, "dsihs0", "dsilink.0");
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clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
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PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
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clk_register_clkdev(clk, "dsihs1", "mcde");
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clk_register_clkdev(clk, "dsihs1", "dsilink.1");
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clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
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PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
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clk_register_clkdev(clk, "dsilp0", "dsilink.0");
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clk_register_clkdev(clk, "dsilp0", "mcde");
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clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
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PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
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clk_register_clkdev(clk, "dsilp1", "dsilink.1");
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clk_register_clkdev(clk, "dsilp1", "mcde");
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clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
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PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
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clk_register_clkdev(clk, "dsilp2", "dsilink.2");
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clk_register_clkdev(clk, "dsilp2", "mcde");
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clk = clk_reg_prcmu_scalable_rate("armss", NULL,
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PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
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clk_register_clkdev(clk, "armss", NULL);
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clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
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CLK_IGNORE_UNUSED, 1, 2);
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clk_register_clkdev(clk, NULL, "smp_twd");
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/*
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* FIXME: Add special handled PRCMU clocks here:
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* 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
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* 2. ab9540_clkout1yuv, see clkout0yuv
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*/
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/* PRCC P-clocks */
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clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
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BIT(0), 0);
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clk_register_clkdev(clk, "apb_pclk", "uart0");
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clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
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BIT(1), 0);
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clk_register_clkdev(clk, "apb_pclk", "uart1");
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clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
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BIT(2), 0);
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clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1");
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clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
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BIT(3), 0);
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clk_register_clkdev(clk, "apb_pclk", "msp0");
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clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0");
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clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
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BIT(4), 0);
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clk_register_clkdev(clk, "apb_pclk", "msp1");
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clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1");
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clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
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BIT(5), 0);
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clk_register_clkdev(clk, "apb_pclk", "sdi0");
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clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
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BIT(6), 0);
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clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2");
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clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
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BIT(7), 0);
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clk_register_clkdev(clk, NULL, "spi3");
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clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
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BIT(8), 0);
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clk_register_clkdev(clk, "apb_pclk", "slimbus0");
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clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
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BIT(9), 0);
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clk_register_clkdev(clk, NULL, "gpio.0");
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clk_register_clkdev(clk, NULL, "gpio.1");
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clk_register_clkdev(clk, NULL, "gpioblock0");
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clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
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BIT(10), 0);
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clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4");
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clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
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BIT(11), 0);
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clk_register_clkdev(clk, "apb_pclk", "msp3");
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clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3");
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clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
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BIT(0), 0);
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clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3");
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clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
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BIT(1), 0);
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clk_register_clkdev(clk, NULL, "spi2");
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clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
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BIT(2), 0);
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clk_register_clkdev(clk, NULL, "spi1");
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clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
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BIT(3), 0);
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clk_register_clkdev(clk, NULL, "pwl");
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clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
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BIT(4), 0);
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clk_register_clkdev(clk, "apb_pclk", "sdi4");
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clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
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BIT(5), 0);
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clk_register_clkdev(clk, "apb_pclk", "msp2");
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clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2");
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clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
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BIT(6), 0);
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clk_register_clkdev(clk, "apb_pclk", "sdi1");
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clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
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BIT(7), 0);
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clk_register_clkdev(clk, "apb_pclk", "sdi3");
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clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
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BIT(8), 0);
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clk_register_clkdev(clk, NULL, "spi0");
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clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
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BIT(9), 0);
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clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
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clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
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BIT(10), 0);
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clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
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clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
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BIT(11), 0);
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clk_register_clkdev(clk, NULL, "gpio.6");
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clk_register_clkdev(clk, NULL, "gpio.7");
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clk_register_clkdev(clk, NULL, "gpioblock1");
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clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
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BIT(12), 0);
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clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
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BIT(0), 0);
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clk_register_clkdev(clk, "fsmc", NULL);
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clk_register_clkdev(clk, NULL, "smsc911x.0");
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clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
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BIT(1), 0);
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clk_register_clkdev(clk, "apb_pclk", "ssp0");
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clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
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BIT(2), 0);
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clk_register_clkdev(clk, "apb_pclk", "ssp1");
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clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
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BIT(3), 0);
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clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0");
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clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
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BIT(4), 0);
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clk_register_clkdev(clk, "apb_pclk", "sdi2");
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clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
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BIT(5), 0);
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clk_register_clkdev(clk, "apb_pclk", "ske");
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clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");
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clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
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BIT(6), 0);
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clk_register_clkdev(clk, "apb_pclk", "uart2");
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clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
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BIT(7), 0);
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clk_register_clkdev(clk, "apb_pclk", "sdi5");
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clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
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BIT(8), 0);
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clk_register_clkdev(clk, NULL, "gpio.2");
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clk_register_clkdev(clk, NULL, "gpio.3");
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clk_register_clkdev(clk, NULL, "gpio.4");
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clk_register_clkdev(clk, NULL, "gpio.5");
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clk_register_clkdev(clk, NULL, "gpioblock2");
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clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
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BIT(0), 0);
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clk_register_clkdev(clk, "usb", "musb-ux500.0");
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clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
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BIT(1), 0);
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clk_register_clkdev(clk, NULL, "gpio.8");
|
|
clk_register_clkdev(clk, NULL, "gpioblock3");
|
|
|
|
clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
|
|
BIT(0), 0);
|
|
clk_register_clkdev(clk, "apb_pclk", "rng");
|
|
|
|
clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
|
|
BIT(1), 0);
|
|
clk_register_clkdev(clk, NULL, "cryp0");
|
|
clk_register_clkdev(clk, NULL, "cryp1");
|
|
|
|
clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
|
|
BIT(2), 0);
|
|
clk_register_clkdev(clk, NULL, "hash0");
|
|
|
|
clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
|
|
BIT(3), 0);
|
|
clk_register_clkdev(clk, NULL, "pka");
|
|
|
|
clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
|
|
BIT(4), 0);
|
|
clk_register_clkdev(clk, NULL, "hash1");
|
|
|
|
clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
|
|
BIT(5), 0);
|
|
clk_register_clkdev(clk, NULL, "cfgreg");
|
|
|
|
clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
|
|
BIT(6), 0);
|
|
clk_register_clkdev(clk, "apb_pclk", "mtu0");
|
|
|
|
clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
|
|
BIT(7), 0);
|
|
clk_register_clkdev(clk, "apb_pclk", "mtu1");
|
|
|
|
/* PRCC K-clocks
|
|
*
|
|
* FIXME: Some drivers requires PERPIH[n| to be automatically enabled
|
|
* by enabling just the K-clock, even if it is not a valid parent to
|
|
* the K-clock. Until drivers get fixed we might need some kind of
|
|
* "parent muxed join".
|
|
*/
|
|
|
|
/* Periph1 */
|
|
clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
|
|
clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "uart0");
|
|
|
|
clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
|
|
clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "uart1");
|
|
|
|
clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
|
|
clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "nmk-i2c.1");
|
|
|
|
clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
|
|
clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "msp0");
|
|
clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0");
|
|
|
|
clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
|
|
clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "msp1");
|
|
clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1");
|
|
|
|
clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
|
|
clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "sdi0");
|
|
|
|
clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
|
|
clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "nmk-i2c.2");
|
|
|
|
clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
|
|
clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "slimbus0");
|
|
|
|
clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
|
|
clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "nmk-i2c.4");
|
|
|
|
clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
|
|
clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "msp3");
|
|
clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3");
|
|
|
|
/* Periph2 */
|
|
clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
|
|
clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "nmk-i2c.3");
|
|
|
|
clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
|
|
clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "sdi4");
|
|
|
|
clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
|
|
clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "msp2");
|
|
clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2");
|
|
|
|
clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
|
|
clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "sdi1");
|
|
|
|
clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
|
|
clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "sdi3");
|
|
|
|
/* Note that rate is received from parent. */
|
|
clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
|
|
clkrst2_base, BIT(6),
|
|
CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
|
|
clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
|
|
clkrst2_base, BIT(7),
|
|
CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
|
|
|
|
/* Periph3 */
|
|
clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
|
|
clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "ssp0");
|
|
|
|
clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
|
|
clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "ssp1");
|
|
|
|
clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
|
|
clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "nmk-i2c.0");
|
|
|
|
clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
|
|
clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "sdi2");
|
|
|
|
clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
|
|
clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "ske");
|
|
clk_register_clkdev(clk, NULL, "nmk-ske-keypad");
|
|
|
|
clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
|
|
clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "uart2");
|
|
|
|
clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
|
|
clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "sdi5");
|
|
|
|
/* Periph6 */
|
|
clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
|
|
clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
|
|
clk_register_clkdev(clk, NULL, "rng");
|
|
}
|