133 lines
4.3 KiB
C
133 lines
4.3 KiB
C
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MDSS_DSI_PLL_H
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#define __MDSS_DSI_PLL_H
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#define MAX_DSI_PLL_EN_SEQS 10
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#define DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG (0x0020)
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#define DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2 (0x0064)
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#define DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG (0x0068)
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#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1 (0x0070)
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/* Register offsets for 20nm PHY PLL */
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#define MMSS_DSI_PHY_PLL_PLL_CNTRL (0x0014)
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#define MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN (0x002C)
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#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN (0x009C)
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struct lpfr_cfg {
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unsigned long vco_rate;
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u32 r;
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};
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struct dsi_pll_vco_clk {
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unsigned long ref_clk_rate;
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unsigned long min_rate;
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unsigned long max_rate;
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u32 pll_en_seq_cnt;
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struct lpfr_cfg *lpfr_lut;
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u32 lpfr_lut_size;
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void *priv;
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struct clk c;
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int (*pll_enable_seqs[MAX_DSI_PLL_EN_SEQS])
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(struct mdss_pll_resources *dsi_pll_Res);
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};
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struct ssc_params {
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s32 kdiv;
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s64 triang_inc_7_0;
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s64 triang_inc_9_8;
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s64 triang_steps;
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s64 dc_offset;
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s64 freq_seed_7_0;
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s64 freq_seed_15_8;
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};
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struct mdss_dsi_vco_calc {
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s64 sdm_cfg0;
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s64 sdm_cfg1;
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s64 sdm_cfg2;
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s64 sdm_cfg3;
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s64 cal_cfg10;
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s64 cal_cfg11;
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s64 refclk_cfg;
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s64 gen_vco_clk;
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u32 lpfr_lut_res;
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struct ssc_params ssc;
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};
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static inline struct dsi_pll_vco_clk *to_vco_clk(struct clk *clk)
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{
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return container_of(clk, struct dsi_pll_vco_clk, c);
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}
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int dsi_pll_clock_register_hpm(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res);
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int dsi_pll_clock_register_20nm(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res);
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int dsi_pll_clock_register_lpm(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res);
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int dsi_pll_clock_register_8996(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res);
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int set_byte_mux_sel(struct mux_clk *clk, int sel);
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int get_byte_mux_sel(struct mux_clk *clk);
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int dsi_pll_div_prepare(struct clk *c);
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int dsi_pll_mux_prepare(struct clk *c);
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int fixed_4div_set_div(struct div_clk *clk, int div);
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int fixed_4div_get_div(struct div_clk *clk);
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int digital_set_div(struct div_clk *clk, int div);
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int digital_get_div(struct div_clk *clk);
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int analog_set_div(struct div_clk *clk, int div);
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int analog_get_div(struct div_clk *clk);
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int dsi_pll_lock_status(struct mdss_pll_resources *dsi_pll_res);
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int vco_set_rate(struct dsi_pll_vco_clk *vco, unsigned long rate);
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unsigned long vco_get_rate(struct clk *c);
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long vco_round_rate(struct clk *c, unsigned long rate);
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enum handoff vco_handoff(struct clk *c);
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int vco_prepare(struct clk *c);
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void vco_unprepare(struct clk *c);
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/* APIs for 20nm PHY PLL */
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int pll_20nm_vco_set_rate(struct dsi_pll_vco_clk *vco, unsigned long rate);
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int shadow_pll_20nm_vco_set_rate(struct dsi_pll_vco_clk *vco,
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unsigned long rate);
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long pll_20nm_vco_round_rate(struct clk *c, unsigned long rate);
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enum handoff pll_20nm_vco_handoff(struct clk *c);
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int pll_20nm_vco_prepare(struct clk *c);
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void pll_20nm_vco_unprepare(struct clk *c);
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int pll_20nm_vco_enable_seq(struct mdss_pll_resources *dsi_pll_res);
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int set_bypass_lp_div_mux_sel(struct mux_clk *clk, int sel);
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int set_shadow_bypass_lp_div_mux_sel(struct mux_clk *clk, int sel);
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int get_bypass_lp_div_mux_sel(struct mux_clk *clk);
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int fixed_hr_oclk2_set_div(struct div_clk *clk, int div);
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int shadow_fixed_hr_oclk2_set_div(struct div_clk *clk, int div);
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int fixed_hr_oclk2_get_div(struct div_clk *clk);
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int hr_oclk3_set_div(struct div_clk *clk, int div);
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int shadow_hr_oclk3_set_div(struct div_clk *clk, int div);
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int hr_oclk3_get_div(struct div_clk *clk);
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int ndiv_set_div(struct div_clk *clk, int div);
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int shadow_ndiv_set_div(struct div_clk *clk, int div);
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int ndiv_get_div(struct div_clk *clk);
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void __dsi_pll_disable(void __iomem *pll_base);
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int set_mdss_pixel_mux_sel(struct mux_clk *clk, int sel);
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int get_mdss_pixel_mux_sel(struct mux_clk *clk);
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int set_mdss_byte_mux_sel(struct mux_clk *clk, int sel);
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int get_mdss_byte_mux_sel(struct mux_clk *clk);
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#endif
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