329 lines
7.1 KiB
C
329 lines
7.1 KiB
C
/*
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* IOSF-SB MailBox Interface Driver
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* Copyright (c) 2013, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*
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* The IOSF-SB is a fabric bus available on Atom based SOC's that uses a
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* mailbox interface (MBI) to communicate with mutiple devices. This
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* driver implements access to this interface for those platforms that can
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* enumerate the device using PCI.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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#include <linux/debugfs.h>
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#include <linux/capability.h>
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#include <asm/iosf_mbi.h>
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#define PCI_DEVICE_ID_BAYTRAIL 0x0F00
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#define PCI_DEVICE_ID_BRASWELL 0x2280
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#define PCI_DEVICE_ID_QUARK_X1000 0x0958
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static DEFINE_SPINLOCK(iosf_mbi_lock);
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static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
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{
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return (op << 24) | (port << 16) | (offset << 8) | MBI_ENABLE;
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}
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static struct pci_dev *mbi_pdev; /* one mbi device */
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static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr)
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{
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int result;
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if (!mbi_pdev)
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return -ENODEV;
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if (mcrx) {
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result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET,
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mcrx);
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if (result < 0)
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goto fail_read;
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}
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result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr);
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if (result < 0)
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goto fail_read;
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result = pci_read_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
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if (result < 0)
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goto fail_read;
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return 0;
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fail_read:
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dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result);
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return result;
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}
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static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr)
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{
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int result;
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if (!mbi_pdev)
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return -ENODEV;
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result = pci_write_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
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if (result < 0)
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goto fail_write;
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if (mcrx) {
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result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET,
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mcrx);
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if (result < 0)
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goto fail_write;
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}
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result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr);
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if (result < 0)
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goto fail_write;
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return 0;
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fail_write:
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dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result);
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return result;
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}
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int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
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{
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u32 mcr, mcrx;
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unsigned long flags;
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int ret;
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/*Access to the GFX unit is handled by GPU code */
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if (port == BT_MBI_UNIT_GFX) {
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WARN_ON(1);
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return -EPERM;
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}
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mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
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mcrx = offset & MBI_MASK_HI;
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spin_lock_irqsave(&iosf_mbi_lock, flags);
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ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr);
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spin_unlock_irqrestore(&iosf_mbi_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(iosf_mbi_read);
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int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
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{
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u32 mcr, mcrx;
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unsigned long flags;
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int ret;
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/*Access to the GFX unit is handled by GPU code */
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if (port == BT_MBI_UNIT_GFX) {
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WARN_ON(1);
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return -EPERM;
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}
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mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
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mcrx = offset & MBI_MASK_HI;
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spin_lock_irqsave(&iosf_mbi_lock, flags);
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ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr);
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spin_unlock_irqrestore(&iosf_mbi_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(iosf_mbi_write);
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int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
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{
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u32 mcr, mcrx;
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u32 value;
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unsigned long flags;
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int ret;
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/*Access to the GFX unit is handled by GPU code */
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if (port == BT_MBI_UNIT_GFX) {
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WARN_ON(1);
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return -EPERM;
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}
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mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
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mcrx = offset & MBI_MASK_HI;
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spin_lock_irqsave(&iosf_mbi_lock, flags);
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/* Read current mdr value */
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ret = iosf_mbi_pci_read_mdr(mcrx, mcr & MBI_RD_MASK, &value);
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if (ret < 0) {
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spin_unlock_irqrestore(&iosf_mbi_lock, flags);
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return ret;
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}
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/* Apply mask */
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value &= ~mask;
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mdr &= mask;
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value |= mdr;
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/* Write back */
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ret = iosf_mbi_pci_write_mdr(mcrx, mcr | MBI_WR_MASK, value);
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spin_unlock_irqrestore(&iosf_mbi_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(iosf_mbi_modify);
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bool iosf_mbi_available(void)
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{
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/* Mbi isn't hot-pluggable. No remove routine is provided */
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return mbi_pdev;
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}
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EXPORT_SYMBOL(iosf_mbi_available);
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#ifdef CONFIG_IOSF_MBI_DEBUG
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static u32 dbg_mdr;
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static u32 dbg_mcr;
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static u32 dbg_mcrx;
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static int mcr_get(void *data, u64 *val)
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{
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*val = *(u32 *)data;
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return 0;
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}
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static int mcr_set(void *data, u64 val)
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{
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u8 command = ((u32)val & 0xFF000000) >> 24,
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port = ((u32)val & 0x00FF0000) >> 16,
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offset = ((u32)val & 0x0000FF00) >> 8;
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int err;
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*(u32 *)data = val;
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if (!capable(CAP_SYS_RAWIO))
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return -EACCES;
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if (command & 1u)
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err = iosf_mbi_write(port,
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command,
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dbg_mcrx | offset,
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dbg_mdr);
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else
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err = iosf_mbi_read(port,
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command,
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dbg_mcrx | offset,
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&dbg_mdr);
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return err;
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}
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DEFINE_SIMPLE_ATTRIBUTE(iosf_mcr_fops, mcr_get, mcr_set , "%llx\n");
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static struct dentry *iosf_dbg;
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static void iosf_sideband_debug_init(void)
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{
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struct dentry *d;
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iosf_dbg = debugfs_create_dir("iosf_sb", NULL);
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if (IS_ERR_OR_NULL(iosf_dbg))
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return;
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/* mdr */
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d = debugfs_create_x32("mdr", 0660, iosf_dbg, &dbg_mdr);
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if (IS_ERR_OR_NULL(d))
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goto cleanup;
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/* mcrx */
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debugfs_create_x32("mcrx", 0660, iosf_dbg, &dbg_mcrx);
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if (IS_ERR_OR_NULL(d))
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goto cleanup;
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/* mcr - initiates mailbox tranaction */
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debugfs_create_file("mcr", 0660, iosf_dbg, &dbg_mcr, &iosf_mcr_fops);
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if (IS_ERR_OR_NULL(d))
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goto cleanup;
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return;
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cleanup:
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debugfs_remove_recursive(d);
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}
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static void iosf_debugfs_init(void)
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{
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iosf_sideband_debug_init();
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}
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static void iosf_debugfs_remove(void)
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{
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debugfs_remove_recursive(iosf_dbg);
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}
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#else
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static inline void iosf_debugfs_init(void) { }
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static inline void iosf_debugfs_remove(void) { }
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#endif /* CONFIG_IOSF_MBI_DEBUG */
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static int iosf_mbi_probe(struct pci_dev *pdev,
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const struct pci_device_id *unused)
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{
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int ret;
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ret = pci_enable_device(pdev);
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if (ret < 0) {
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dev_err(&pdev->dev, "error: could not enable device\n");
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return ret;
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}
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mbi_pdev = pci_dev_get(pdev);
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return 0;
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}
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static const struct pci_device_id iosf_mbi_pci_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BAYTRAIL) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRASWELL) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_QUARK_X1000) },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);
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static struct pci_driver iosf_mbi_pci_driver = {
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.name = "iosf_mbi_pci",
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.probe = iosf_mbi_probe,
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.id_table = iosf_mbi_pci_ids,
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};
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static int __init iosf_mbi_init(void)
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{
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iosf_debugfs_init();
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return pci_register_driver(&iosf_mbi_pci_driver);
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}
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static void __exit iosf_mbi_exit(void)
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{
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iosf_debugfs_remove();
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pci_unregister_driver(&iosf_mbi_pci_driver);
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if (mbi_pdev) {
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pci_dev_put(mbi_pdev);
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mbi_pdev = NULL;
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}
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}
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module_init(iosf_mbi_init);
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module_exit(iosf_mbi_exit);
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MODULE_AUTHOR("David E. Box <david.e.box@linux.intel.com>");
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MODULE_DESCRIPTION("IOSF Mailbox Interface accessor");
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MODULE_LICENSE("GPL v2");
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