681 lines
20 KiB
C
681 lines
20 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV architectural definitions
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*
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* Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_X86_UV_UV_HUB_H
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#define _ASM_X86_UV_UV_HUB_H
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#ifdef CONFIG_X86_64
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#include <linux/numa.h>
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#include <linux/percpu.h>
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#include <linux/timer.h>
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#include <linux/io.h>
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#include <asm/types.h>
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#include <asm/percpu.h>
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#include <asm/uv/uv_mmrs.h>
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#include <asm/irq_vectors.h>
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#include <asm/io_apic.h>
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/*
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* Addressing Terminology
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*
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* M - The low M bits of a physical address represent the offset
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* into the blade local memory. RAM memory on a blade is physically
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* contiguous (although various IO spaces may punch holes in
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* it)..
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*
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* N - Number of bits in the node portion of a socket physical
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* address.
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*
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* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
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* routers always have low bit of 1, C/MBricks have low bit
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* equal to 0. Most addressing macros that target UV hub chips
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* right shift the NASID by 1 to exclude the always-zero bit.
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* NASIDs contain up to 15 bits.
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*
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* GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
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* of nasids.
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*
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* PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
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* of the nasid for socket usage.
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*
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* GPA - (global physical address) a socket physical address converted
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* so that it can be used by the GRU as a global address. Socket
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* physical addresses 1) need additional NASID (node) bits added
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* to the high end of the address, and 2) unaliased if the
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* partition does not have a physical address 0. In addition, on
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* UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40.
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*
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*
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* NumaLink Global Physical Address Format:
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* +--------------------------------+---------------------+
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* |00..000| GNODE | NodeOffset |
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* +--------------------------------+---------------------+
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* |<-------53 - M bits --->|<--------M bits ----->
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*
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* M - number of node offset bits (35 .. 40)
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*
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*
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* Memory/UV-HUB Processor Socket Address Format:
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* +----------------+---------------+---------------------+
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* |00..000000000000| PNODE | NodeOffset |
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* +----------------+---------------+---------------------+
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* <--- N bits --->|<--------M bits ----->
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*
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* M - number of node offset bits (35 .. 40)
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* N - number of PNODE bits (0 .. 10)
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*
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* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
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* The actual values are configuration dependent and are set at
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* boot time. M & N values are set by the hardware/BIOS at boot.
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*
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*
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* APICID format
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* NOTE!!!!!! This is the current format of the APICID. However, code
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* should assume that this will change in the future. Use functions
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* in this file for all APICID bit manipulations and conversion.
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*
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* 1111110000000000
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* 5432109876543210
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* pppppppppplc0cch Nehalem-EX (12 bits in hdw reg)
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* ppppppppplcc0cch Westmere-EX (12 bits in hdw reg)
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* pppppppppppcccch SandyBridge (15 bits in hdw reg)
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* sssssssssss
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*
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* p = pnode bits
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* l = socket number on board
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* c = core
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* h = hyperthread
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* s = bits that are in the SOCKET_ID CSR
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*
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* Note: Processor may support fewer bits in the APICID register. The ACPI
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* tables hold all 16 bits. Software needs to be aware of this.
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*
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* Unless otherwise specified, all references to APICID refer to
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* the FULL value contained in ACPI tables, not the subset in the
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* processor APICID register.
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*/
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/*
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* Maximum number of bricks in all partitions and in all coherency domains.
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* This is the total number of bricks accessible in the numalink fabric. It
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* includes all C & M bricks. Routers are NOT included.
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*
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* This value is also the value of the maximum number of non-router NASIDs
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* in the numalink fabric.
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*
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* NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
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*/
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#define UV_MAX_NUMALINK_BLADES 16384
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/*
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* Maximum number of C/Mbricks within a software SSI (hardware may support
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* more).
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*/
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#define UV_MAX_SSI_BLADES 256
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/*
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* The largest possible NASID of a C or M brick (+ 2)
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*/
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#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2)
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struct uv_scir_s {
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struct timer_list timer;
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unsigned long offset;
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unsigned long last;
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unsigned long idle_on;
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unsigned long idle_off;
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unsigned char state;
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unsigned char enabled;
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};
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/*
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* The following defines attributes of the HUB chip. These attributes are
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* frequently referenced and are kept in the per-cpu data areas of each cpu.
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* They are kept together in a struct to minimize cache misses.
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*/
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struct uv_hub_info_s {
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unsigned long global_mmr_base;
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unsigned long gpa_mask;
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unsigned int gnode_extra;
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unsigned char hub_revision;
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unsigned char apic_pnode_shift;
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unsigned char m_shift;
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unsigned char n_lshift;
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unsigned long gnode_upper;
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unsigned long lowmem_remap_top;
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unsigned long lowmem_remap_base;
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unsigned short pnode;
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unsigned short pnode_mask;
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unsigned short coherency_domain_number;
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unsigned short numa_blade_id;
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unsigned char blade_processor_id;
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unsigned char m_val;
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unsigned char n_val;
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struct uv_scir_s scir;
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};
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DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
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#define uv_hub_info this_cpu_ptr(&__uv_hub_info)
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#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
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/*
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* Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2
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* hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE.
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* This is a software convention - NOT the hardware revision numbers in
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* the hub chip.
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*/
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#define UV1_HUB_REVISION_BASE 1
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#define UV2_HUB_REVISION_BASE 3
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#define UV3_HUB_REVISION_BASE 5
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static inline int is_uv1_hub(void)
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{
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return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;
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}
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static inline int is_uv2_hub(void)
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{
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return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) &&
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(uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE));
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}
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static inline int is_uv3_hub(void)
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{
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return uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE;
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}
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static inline int is_uv_hub(void)
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{
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return uv_hub_info->hub_revision;
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}
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/* code common to uv2 and uv3 only */
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static inline int is_uvx_hub(void)
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{
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return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE;
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}
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union uvh_apicid {
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unsigned long v;
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struct uvh_apicid_s {
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unsigned long local_apic_mask : 24;
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unsigned long local_apic_shift : 5;
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unsigned long unused1 : 3;
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unsigned long pnode_mask : 24;
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unsigned long pnode_shift : 5;
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unsigned long unused2 : 3;
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} s;
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};
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/*
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* Local & Global MMR space macros.
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* Note: macros are intended to be used ONLY by inline functions
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* in this file - not by other kernel code.
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* n - NASID (full 15-bit global nasid)
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* g - GNODE (full 15-bit global nasid, right shifted 1)
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* p - PNODE (local part of nsids, right shifted 1)
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*/
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#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
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#define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra)
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#define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1)
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#define UV1_LOCAL_MMR_BASE 0xf4000000UL
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#define UV1_GLOBAL_MMR32_BASE 0xf8000000UL
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#define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
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#define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
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#define UV2_LOCAL_MMR_BASE 0xfa000000UL
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#define UV2_GLOBAL_MMR32_BASE 0xfc000000UL
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#define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
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#define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
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#define UV3_LOCAL_MMR_BASE 0xfa000000UL
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#define UV3_GLOBAL_MMR32_BASE 0xfc000000UL
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#define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
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#define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
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#define UV_LOCAL_MMR_BASE (is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \
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(is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \
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UV3_LOCAL_MMR_BASE))
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#define UV_GLOBAL_MMR32_BASE (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE :\
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(is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE :\
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UV3_GLOBAL_MMR32_BASE))
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#define UV_LOCAL_MMR_SIZE (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
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(is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \
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UV3_LOCAL_MMR_SIZE))
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#define UV_GLOBAL_MMR32_SIZE (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\
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(is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE :\
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UV3_GLOBAL_MMR32_SIZE))
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#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
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#define UV_GLOBAL_GRU_MMR_BASE 0x4000000
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#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
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#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
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#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
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#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
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(((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
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#define UVH_APICID 0x002D0E00L
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#define UV_APIC_PNODE_SHIFT 6
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#define UV_APICID_HIBIT_MASK 0xffff0000
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/* Local Bus from cpu's perspective */
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#define LOCAL_BUS_BASE 0x1c00000
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#define LOCAL_BUS_SIZE (4 * 1024 * 1024)
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/*
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* System Controller Interface Reg
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*
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* Note there are NO leds on a UV system. This register is only
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* used by the system controller to monitor system-wide operation.
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* There are 64 regs per node. With Nahelem cpus (2 cores per node,
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* 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
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* a node.
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*
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* The window is located at top of ACPI MMR space
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*/
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#define SCIR_WINDOW_COUNT 64
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#define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
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LOCAL_BUS_SIZE - \
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SCIR_WINDOW_COUNT)
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#define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */
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#define SCIR_CPU_ACTIVITY 0x02 /* not idle */
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#define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */
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/* Loop through all installed blades */
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#define for_each_possible_blade(bid) \
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for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
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/*
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* Macros for converting between kernel virtual addresses, socket local physical
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* addresses, and UV global physical addresses.
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* Note: use the standard __pa() & __va() macros for converting
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* between socket virtual and socket physical addresses.
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*/
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/* socket phys RAM --> UV global physical address */
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static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
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{
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if (paddr < uv_hub_info->lowmem_remap_top)
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paddr |= uv_hub_info->lowmem_remap_base;
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paddr |= uv_hub_info->gnode_upper;
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paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
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((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift);
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return paddr;
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}
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/* socket virtual --> UV global physical address */
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static inline unsigned long uv_gpa(void *v)
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{
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return uv_soc_phys_ram_to_gpa(__pa(v));
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}
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/* Top two bits indicate the requested address is in MMR space. */
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static inline int
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uv_gpa_in_mmr_space(unsigned long gpa)
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{
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return (gpa >> 62) == 0x3UL;
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}
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/* UV global physical address --> socket phys RAM */
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static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
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{
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unsigned long paddr;
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unsigned long remap_base = uv_hub_info->lowmem_remap_base;
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unsigned long remap_top = uv_hub_info->lowmem_remap_top;
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gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
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((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
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paddr = gpa & uv_hub_info->gpa_mask;
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if (paddr >= remap_base && paddr < remap_base + remap_top)
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paddr -= remap_base;
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return paddr;
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}
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/* gpa -> pnode */
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static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
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{
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return gpa >> uv_hub_info->n_lshift;
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}
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/* gpa -> pnode */
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static inline int uv_gpa_to_pnode(unsigned long gpa)
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{
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unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1;
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return uv_gpa_to_gnode(gpa) & n_mask;
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}
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/* gpa -> node offset*/
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static inline unsigned long uv_gpa_to_offset(unsigned long gpa)
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{
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return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift;
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}
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/* pnode, offset --> socket virtual */
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static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
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{
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return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
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}
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/*
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* Extract a PNODE from an APICID (full apicid, not processor subset)
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*/
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static inline int uv_apicid_to_pnode(int apicid)
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{
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return (apicid >> uv_hub_info->apic_pnode_shift);
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}
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/*
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* Convert an apicid to the socket number on the blade
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*/
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static inline int uv_apicid_to_socket(int apicid)
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{
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if (is_uv1_hub())
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return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;
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else
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return 0;
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}
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/*
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* Access global MMRs using the low memory MMR32 space. This region supports
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* faster MMR access but not all MMRs are accessible in this space.
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*/
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static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset)
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{
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return __va(UV_GLOBAL_MMR32_BASE |
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UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
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}
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static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val)
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{
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writeq(val, uv_global_mmr32_address(pnode, offset));
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}
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static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset)
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{
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return readq(uv_global_mmr32_address(pnode, offset));
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}
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/*
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* Access Global MMR space using the MMR space located at the top of physical
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* memory.
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*/
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static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset)
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{
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return __va(UV_GLOBAL_MMR64_BASE |
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UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
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}
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static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val)
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{
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writeq(val, uv_global_mmr64_address(pnode, offset));
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}
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static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset)
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{
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return readq(uv_global_mmr64_address(pnode, offset));
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}
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/*
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* Global MMR space addresses when referenced by the GRU. (GRU does
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* NOT use socket addressing).
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*/
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static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset)
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{
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return UV_GLOBAL_GRU_MMR_BASE | offset |
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((unsigned long)pnode << uv_hub_info->m_val);
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}
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static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
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{
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writeb(val, uv_global_mmr64_address(pnode, offset));
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}
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static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset)
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{
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return readb(uv_global_mmr64_address(pnode, offset));
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}
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/*
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* Access hub local MMRs. Faster than using global space but only local MMRs
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* are accessible.
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*/
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static inline unsigned long *uv_local_mmr_address(unsigned long offset)
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{
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return __va(UV_LOCAL_MMR_BASE | offset);
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}
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static inline unsigned long uv_read_local_mmr(unsigned long offset)
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{
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return readq(uv_local_mmr_address(offset));
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}
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static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
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{
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writeq(val, uv_local_mmr_address(offset));
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}
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static inline unsigned char uv_read_local_mmr8(unsigned long offset)
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{
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return readb(uv_local_mmr_address(offset));
|
|
}
|
|
|
|
static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
|
|
{
|
|
writeb(val, uv_local_mmr_address(offset));
|
|
}
|
|
|
|
/*
|
|
* Structures and definitions for converting between cpu, node, pnode, and blade
|
|
* numbers.
|
|
*/
|
|
struct uv_blade_info {
|
|
unsigned short nr_possible_cpus;
|
|
unsigned short nr_online_cpus;
|
|
unsigned short pnode;
|
|
short memory_nid;
|
|
spinlock_t nmi_lock; /* obsolete, see uv_hub_nmi */
|
|
unsigned long nmi_count; /* obsolete, see uv_hub_nmi */
|
|
};
|
|
extern struct uv_blade_info *uv_blade_info;
|
|
extern short *uv_node_to_blade;
|
|
extern short *uv_cpu_to_blade;
|
|
extern short uv_possible_blades;
|
|
|
|
/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
|
|
static inline int uv_blade_processor_id(void)
|
|
{
|
|
return uv_hub_info->blade_processor_id;
|
|
}
|
|
|
|
/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
|
|
static inline int uv_numa_blade_id(void)
|
|
{
|
|
return uv_hub_info->numa_blade_id;
|
|
}
|
|
|
|
/* Convert a cpu number to the the UV blade number */
|
|
static inline int uv_cpu_to_blade_id(int cpu)
|
|
{
|
|
return uv_cpu_to_blade[cpu];
|
|
}
|
|
|
|
/* Convert linux node number to the UV blade number */
|
|
static inline int uv_node_to_blade_id(int nid)
|
|
{
|
|
return uv_node_to_blade[nid];
|
|
}
|
|
|
|
/* Convert a blade id to the PNODE of the blade */
|
|
static inline int uv_blade_to_pnode(int bid)
|
|
{
|
|
return uv_blade_info[bid].pnode;
|
|
}
|
|
|
|
/* Nid of memory node on blade. -1 if no blade-local memory */
|
|
static inline int uv_blade_to_memory_nid(int bid)
|
|
{
|
|
return uv_blade_info[bid].memory_nid;
|
|
}
|
|
|
|
/* Determine the number of possible cpus on a blade */
|
|
static inline int uv_blade_nr_possible_cpus(int bid)
|
|
{
|
|
return uv_blade_info[bid].nr_possible_cpus;
|
|
}
|
|
|
|
/* Determine the number of online cpus on a blade */
|
|
static inline int uv_blade_nr_online_cpus(int bid)
|
|
{
|
|
return uv_blade_info[bid].nr_online_cpus;
|
|
}
|
|
|
|
/* Convert a cpu id to the PNODE of the blade containing the cpu */
|
|
static inline int uv_cpu_to_pnode(int cpu)
|
|
{
|
|
return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
|
|
}
|
|
|
|
/* Convert a linux node number to the PNODE of the blade */
|
|
static inline int uv_node_to_pnode(int nid)
|
|
{
|
|
return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
|
|
}
|
|
|
|
/* Maximum possible number of blades */
|
|
static inline int uv_num_possible_blades(void)
|
|
{
|
|
return uv_possible_blades;
|
|
}
|
|
|
|
/* Per Hub NMI support */
|
|
extern void uv_nmi_setup(void);
|
|
|
|
/* BMC sets a bit this MMR non-zero before sending an NMI */
|
|
#define UVH_NMI_MMR UVH_SCRATCH5
|
|
#define UVH_NMI_MMR_CLEAR UVH_SCRATCH5_ALIAS
|
|
#define UVH_NMI_MMR_SHIFT 63
|
|
#define UVH_NMI_MMR_TYPE "SCRATCH5"
|
|
|
|
/* Newer SMM NMI handler, not present in all systems */
|
|
#define UVH_NMI_MMRX UVH_EVENT_OCCURRED0
|
|
#define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS
|
|
#define UVH_NMI_MMRX_SHIFT (is_uv1_hub() ? \
|
|
UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :\
|
|
UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT)
|
|
#define UVH_NMI_MMRX_TYPE "EXTIO_INT0"
|
|
|
|
/* Non-zero indicates newer SMM NMI handler present */
|
|
#define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST
|
|
|
|
/* Indicates to BIOS that we want to use the newer SMM NMI handler */
|
|
#define UVH_NMI_MMRX_REQ UVH_SCRATCH5_ALIAS_2
|
|
#define UVH_NMI_MMRX_REQ_SHIFT 62
|
|
|
|
struct uv_hub_nmi_s {
|
|
raw_spinlock_t nmi_lock;
|
|
atomic_t in_nmi; /* flag this node in UV NMI IRQ */
|
|
atomic_t cpu_owner; /* last locker of this struct */
|
|
atomic_t read_mmr_count; /* count of MMR reads */
|
|
atomic_t nmi_count; /* count of true UV NMIs */
|
|
unsigned long nmi_value; /* last value read from NMI MMR */
|
|
};
|
|
|
|
struct uv_cpu_nmi_s {
|
|
struct uv_hub_nmi_s *hub;
|
|
int state;
|
|
int pinging;
|
|
int queries;
|
|
int pings;
|
|
};
|
|
|
|
DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
|
|
|
|
#define uv_hub_nmi (uv_cpu_nmi.hub)
|
|
#define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu))
|
|
#define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub)
|
|
|
|
/* uv_cpu_nmi_states */
|
|
#define UV_NMI_STATE_OUT 0
|
|
#define UV_NMI_STATE_IN 1
|
|
#define UV_NMI_STATE_DUMP 2
|
|
#define UV_NMI_STATE_DUMP_DONE 3
|
|
|
|
/* Update SCIR state */
|
|
static inline void uv_set_scir_bits(unsigned char value)
|
|
{
|
|
if (uv_hub_info->scir.state != value) {
|
|
uv_hub_info->scir.state = value;
|
|
uv_write_local_mmr8(uv_hub_info->scir.offset, value);
|
|
}
|
|
}
|
|
|
|
static inline unsigned long uv_scir_offset(int apicid)
|
|
{
|
|
return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f);
|
|
}
|
|
|
|
static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
|
|
{
|
|
if (uv_cpu_hub_info(cpu)->scir.state != value) {
|
|
uv_write_global_mmr8(uv_cpu_to_pnode(cpu),
|
|
uv_cpu_hub_info(cpu)->scir.offset, value);
|
|
uv_cpu_hub_info(cpu)->scir.state = value;
|
|
}
|
|
}
|
|
|
|
extern unsigned int uv_apicid_hibits;
|
|
static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)
|
|
{
|
|
apicid |= uv_apicid_hibits;
|
|
return (1UL << UVH_IPI_INT_SEND_SHFT) |
|
|
((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
|
|
(mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
|
|
(vector << UVH_IPI_INT_VECTOR_SHFT);
|
|
}
|
|
|
|
static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
|
|
{
|
|
unsigned long val;
|
|
unsigned long dmode = dest_Fixed;
|
|
|
|
if (vector == NMI_VECTOR)
|
|
dmode = dest_NMI;
|
|
|
|
val = uv_hub_ipi_value(apicid, vector, dmode);
|
|
uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
|
|
}
|
|
|
|
/*
|
|
* Get the minimum revision number of the hub chips within the partition.
|
|
* 1 - UV1 rev 1.0 initial silicon
|
|
* 2 - UV1 rev 2.0 production silicon
|
|
* 3 - UV2 rev 1.0 initial silicon
|
|
* 5 - UV3 rev 1.0 initial silicon
|
|
*/
|
|
static inline int uv_get_min_hub_revision_id(void)
|
|
{
|
|
return uv_hub_info->hub_revision;
|
|
}
|
|
|
|
#endif /* CONFIG_X86_64 */
|
|
#endif /* _ASM_X86_UV_UV_HUB_H */
|