393 lines
10 KiB
C
393 lines
10 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2012 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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#ifndef __CVMX_STXX_DEFS_H__
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#define __CVMX_STXX_DEFS_H__
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#define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
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#define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
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#define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
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union cvmx_stxx_arb_ctl {
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uint64_t u64;
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struct cvmx_stxx_arb_ctl_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_6_63:58;
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uint64_t mintrn:1;
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uint64_t reserved_4_4:1;
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uint64_t igntpa:1;
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uint64_t reserved_0_2:3;
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#else
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uint64_t reserved_0_2:3;
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uint64_t igntpa:1;
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uint64_t reserved_4_4:1;
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uint64_t mintrn:1;
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uint64_t reserved_6_63:58;
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#endif
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} s;
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struct cvmx_stxx_arb_ctl_s cn38xx;
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struct cvmx_stxx_arb_ctl_s cn38xxp2;
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struct cvmx_stxx_arb_ctl_s cn58xx;
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struct cvmx_stxx_arb_ctl_s cn58xxp1;
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};
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union cvmx_stxx_bckprs_cnt {
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uint64_t u64;
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struct cvmx_stxx_bckprs_cnt_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_32_63:32;
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uint64_t cnt:32;
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#else
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uint64_t cnt:32;
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uint64_t reserved_32_63:32;
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#endif
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} s;
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struct cvmx_stxx_bckprs_cnt_s cn38xx;
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struct cvmx_stxx_bckprs_cnt_s cn38xxp2;
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struct cvmx_stxx_bckprs_cnt_s cn58xx;
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struct cvmx_stxx_bckprs_cnt_s cn58xxp1;
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};
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union cvmx_stxx_com_ctl {
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uint64_t u64;
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struct cvmx_stxx_com_ctl_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_4_63:60;
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uint64_t st_en:1;
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uint64_t reserved_1_2:2;
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uint64_t inf_en:1;
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#else
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uint64_t inf_en:1;
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uint64_t reserved_1_2:2;
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uint64_t st_en:1;
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uint64_t reserved_4_63:60;
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#endif
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} s;
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struct cvmx_stxx_com_ctl_s cn38xx;
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struct cvmx_stxx_com_ctl_s cn38xxp2;
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struct cvmx_stxx_com_ctl_s cn58xx;
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struct cvmx_stxx_com_ctl_s cn58xxp1;
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};
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union cvmx_stxx_dip_cnt {
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uint64_t u64;
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struct cvmx_stxx_dip_cnt_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_8_63:56;
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uint64_t frmmax:4;
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uint64_t dipmax:4;
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#else
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uint64_t dipmax:4;
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uint64_t frmmax:4;
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uint64_t reserved_8_63:56;
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#endif
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} s;
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struct cvmx_stxx_dip_cnt_s cn38xx;
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struct cvmx_stxx_dip_cnt_s cn38xxp2;
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struct cvmx_stxx_dip_cnt_s cn58xx;
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struct cvmx_stxx_dip_cnt_s cn58xxp1;
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};
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union cvmx_stxx_ign_cal {
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uint64_t u64;
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struct cvmx_stxx_ign_cal_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_16_63:48;
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uint64_t igntpa:16;
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#else
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uint64_t igntpa:16;
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uint64_t reserved_16_63:48;
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#endif
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} s;
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struct cvmx_stxx_ign_cal_s cn38xx;
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struct cvmx_stxx_ign_cal_s cn38xxp2;
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struct cvmx_stxx_ign_cal_s cn58xx;
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struct cvmx_stxx_ign_cal_s cn58xxp1;
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};
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union cvmx_stxx_int_msk {
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uint64_t u64;
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struct cvmx_stxx_int_msk_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_8_63:56;
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uint64_t frmerr:1;
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uint64_t unxfrm:1;
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uint64_t nosync:1;
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uint64_t diperr:1;
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uint64_t datovr:1;
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uint64_t ovrbst:1;
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uint64_t calpar1:1;
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uint64_t calpar0:1;
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#else
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uint64_t calpar0:1;
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uint64_t calpar1:1;
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uint64_t ovrbst:1;
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uint64_t datovr:1;
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uint64_t diperr:1;
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uint64_t nosync:1;
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uint64_t unxfrm:1;
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uint64_t frmerr:1;
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uint64_t reserved_8_63:56;
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#endif
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} s;
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struct cvmx_stxx_int_msk_s cn38xx;
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struct cvmx_stxx_int_msk_s cn38xxp2;
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struct cvmx_stxx_int_msk_s cn58xx;
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struct cvmx_stxx_int_msk_s cn58xxp1;
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};
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union cvmx_stxx_int_reg {
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uint64_t u64;
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struct cvmx_stxx_int_reg_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_9_63:55;
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uint64_t syncerr:1;
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uint64_t frmerr:1;
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uint64_t unxfrm:1;
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uint64_t nosync:1;
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uint64_t diperr:1;
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uint64_t datovr:1;
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uint64_t ovrbst:1;
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uint64_t calpar1:1;
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uint64_t calpar0:1;
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#else
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uint64_t calpar0:1;
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uint64_t calpar1:1;
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uint64_t ovrbst:1;
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uint64_t datovr:1;
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uint64_t diperr:1;
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uint64_t nosync:1;
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uint64_t unxfrm:1;
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uint64_t frmerr:1;
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uint64_t syncerr:1;
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uint64_t reserved_9_63:55;
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#endif
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} s;
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struct cvmx_stxx_int_reg_s cn38xx;
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struct cvmx_stxx_int_reg_s cn38xxp2;
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struct cvmx_stxx_int_reg_s cn58xx;
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struct cvmx_stxx_int_reg_s cn58xxp1;
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};
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union cvmx_stxx_int_sync {
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uint64_t u64;
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struct cvmx_stxx_int_sync_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_8_63:56;
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uint64_t frmerr:1;
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uint64_t unxfrm:1;
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uint64_t nosync:1;
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uint64_t diperr:1;
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uint64_t datovr:1;
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uint64_t ovrbst:1;
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uint64_t calpar1:1;
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uint64_t calpar0:1;
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#else
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uint64_t calpar0:1;
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uint64_t calpar1:1;
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uint64_t ovrbst:1;
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uint64_t datovr:1;
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uint64_t diperr:1;
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uint64_t nosync:1;
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uint64_t unxfrm:1;
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uint64_t frmerr:1;
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uint64_t reserved_8_63:56;
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#endif
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} s;
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struct cvmx_stxx_int_sync_s cn38xx;
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struct cvmx_stxx_int_sync_s cn38xxp2;
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struct cvmx_stxx_int_sync_s cn58xx;
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struct cvmx_stxx_int_sync_s cn58xxp1;
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};
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union cvmx_stxx_min_bst {
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uint64_t u64;
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struct cvmx_stxx_min_bst_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_9_63:55;
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uint64_t minb:9;
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#else
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uint64_t minb:9;
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uint64_t reserved_9_63:55;
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#endif
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} s;
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struct cvmx_stxx_min_bst_s cn38xx;
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struct cvmx_stxx_min_bst_s cn38xxp2;
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struct cvmx_stxx_min_bst_s cn58xx;
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struct cvmx_stxx_min_bst_s cn58xxp1;
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};
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union cvmx_stxx_spi4_calx {
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uint64_t u64;
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struct cvmx_stxx_spi4_calx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_17_63:47;
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uint64_t oddpar:1;
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uint64_t prt3:4;
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uint64_t prt2:4;
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uint64_t prt1:4;
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uint64_t prt0:4;
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#else
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uint64_t prt0:4;
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uint64_t prt1:4;
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uint64_t prt2:4;
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uint64_t prt3:4;
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uint64_t oddpar:1;
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uint64_t reserved_17_63:47;
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#endif
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} s;
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struct cvmx_stxx_spi4_calx_s cn38xx;
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struct cvmx_stxx_spi4_calx_s cn38xxp2;
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struct cvmx_stxx_spi4_calx_s cn58xx;
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struct cvmx_stxx_spi4_calx_s cn58xxp1;
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};
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union cvmx_stxx_spi4_dat {
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uint64_t u64;
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struct cvmx_stxx_spi4_dat_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_32_63:32;
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uint64_t alpha:16;
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uint64_t max_t:16;
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#else
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uint64_t max_t:16;
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uint64_t alpha:16;
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uint64_t reserved_32_63:32;
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#endif
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} s;
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struct cvmx_stxx_spi4_dat_s cn38xx;
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struct cvmx_stxx_spi4_dat_s cn38xxp2;
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struct cvmx_stxx_spi4_dat_s cn58xx;
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struct cvmx_stxx_spi4_dat_s cn58xxp1;
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};
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union cvmx_stxx_spi4_stat {
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uint64_t u64;
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struct cvmx_stxx_spi4_stat_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_16_63:48;
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uint64_t m:8;
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uint64_t reserved_7_7:1;
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uint64_t len:7;
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#else
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uint64_t len:7;
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uint64_t reserved_7_7:1;
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uint64_t m:8;
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uint64_t reserved_16_63:48;
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#endif
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} s;
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struct cvmx_stxx_spi4_stat_s cn38xx;
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struct cvmx_stxx_spi4_stat_s cn38xxp2;
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struct cvmx_stxx_spi4_stat_s cn58xx;
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struct cvmx_stxx_spi4_stat_s cn58xxp1;
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};
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union cvmx_stxx_stat_bytes_hi {
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uint64_t u64;
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struct cvmx_stxx_stat_bytes_hi_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_32_63:32;
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uint64_t cnt:32;
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#else
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uint64_t cnt:32;
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uint64_t reserved_32_63:32;
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#endif
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} s;
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struct cvmx_stxx_stat_bytes_hi_s cn38xx;
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struct cvmx_stxx_stat_bytes_hi_s cn38xxp2;
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struct cvmx_stxx_stat_bytes_hi_s cn58xx;
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struct cvmx_stxx_stat_bytes_hi_s cn58xxp1;
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};
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union cvmx_stxx_stat_bytes_lo {
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uint64_t u64;
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struct cvmx_stxx_stat_bytes_lo_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_32_63:32;
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uint64_t cnt:32;
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#else
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uint64_t cnt:32;
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uint64_t reserved_32_63:32;
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#endif
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} s;
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struct cvmx_stxx_stat_bytes_lo_s cn38xx;
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struct cvmx_stxx_stat_bytes_lo_s cn38xxp2;
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struct cvmx_stxx_stat_bytes_lo_s cn58xx;
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struct cvmx_stxx_stat_bytes_lo_s cn58xxp1;
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};
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union cvmx_stxx_stat_ctl {
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uint64_t u64;
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struct cvmx_stxx_stat_ctl_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_5_63:59;
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uint64_t clr:1;
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uint64_t bckprs:4;
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#else
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uint64_t bckprs:4;
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uint64_t clr:1;
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uint64_t reserved_5_63:59;
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#endif
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} s;
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struct cvmx_stxx_stat_ctl_s cn38xx;
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struct cvmx_stxx_stat_ctl_s cn38xxp2;
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struct cvmx_stxx_stat_ctl_s cn58xx;
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struct cvmx_stxx_stat_ctl_s cn58xxp1;
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};
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union cvmx_stxx_stat_pkt_xmt {
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uint64_t u64;
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struct cvmx_stxx_stat_pkt_xmt_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_32_63:32;
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uint64_t cnt:32;
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#else
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uint64_t cnt:32;
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uint64_t reserved_32_63:32;
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#endif
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} s;
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struct cvmx_stxx_stat_pkt_xmt_s cn38xx;
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struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2;
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struct cvmx_stxx_stat_pkt_xmt_s cn58xx;
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struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1;
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};
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#endif
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