344 lines
11 KiB
C
344 lines
11 KiB
C
/*
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*
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* Macros for external SMP-safe access to the PMC MSP71xx reference
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* board GPIO pins
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*
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* Copyright 2010 PMC-Sierra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __MSP_GPIO_MACROS_H__
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#define __MSP_GPIO_MACROS_H__
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#include <msp_regops.h>
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#include <msp_regs.h>
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#ifdef CONFIG_PMC_MSP7120_GW
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#define MSP_NUM_GPIOS 20
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#else
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#define MSP_NUM_GPIOS 28
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#endif
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/* -- GPIO Enumerations -- */
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enum msp_gpio_data {
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MSP_GPIO_LO = 0,
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MSP_GPIO_HI = 1,
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MSP_GPIO_NONE, /* Special - Means pin is out of range */
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MSP_GPIO_TOGGLE, /* Special - Sets pin to opposite */
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};
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enum msp_gpio_mode {
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MSP_GPIO_INPUT = 0x0,
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/* MSP_GPIO_ INTERRUPT = 0x1, Not supported yet */
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MSP_GPIO_UART_INPUT = 0x2, /* Only GPIO 4 or 5 */
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MSP_GPIO_OUTPUT = 0x8,
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MSP_GPIO_UART_OUTPUT = 0x9, /* Only GPIO 2 or 3 */
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MSP_GPIO_PERIF_TIMERA = 0x9, /* Only GPIO 0 or 1 */
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MSP_GPIO_PERIF_TIMERB = 0xa, /* Only GPIO 0 or 1 */
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MSP_GPIO_UNKNOWN = 0xb, /* No such GPIO or mode */
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};
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/* -- Static Tables -- */
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/* Maps pins to data register */
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static volatile u32 * const MSP_GPIO_DATA_REGISTER[] = {
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/* GPIO 0 and 1 on the first register */
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GPIO_DATA1_REG, GPIO_DATA1_REG,
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/* GPIO 2, 3, 4, and 5 on the second register */
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GPIO_DATA2_REG, GPIO_DATA2_REG, GPIO_DATA2_REG, GPIO_DATA2_REG,
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/* GPIO 6, 7, 8, and 9 on the third register */
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GPIO_DATA3_REG, GPIO_DATA3_REG, GPIO_DATA3_REG, GPIO_DATA3_REG,
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/* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */
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GPIO_DATA4_REG, GPIO_DATA4_REG, GPIO_DATA4_REG, GPIO_DATA4_REG,
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GPIO_DATA4_REG, GPIO_DATA4_REG,
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/* GPIO 16 - 23 on the first strange EXTENDED register */
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EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
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EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
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EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
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/* GPIO 24 - 27 on the second strange EXTENDED register */
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EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG,
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EXTENDED_GPIO2_REG,
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};
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/* Maps pins to mode register */
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static volatile u32 * const MSP_GPIO_MODE_REGISTER[] = {
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/* GPIO 0 and 1 on the first register */
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GPIO_CFG1_REG, GPIO_CFG1_REG,
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/* GPIO 2, 3, 4, and 5 on the second register */
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GPIO_CFG2_REG, GPIO_CFG2_REG, GPIO_CFG2_REG, GPIO_CFG2_REG,
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/* GPIO 6, 7, 8, and 9 on the third register */
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GPIO_CFG3_REG, GPIO_CFG3_REG, GPIO_CFG3_REG, GPIO_CFG3_REG,
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/* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */
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GPIO_CFG4_REG, GPIO_CFG4_REG, GPIO_CFG4_REG, GPIO_CFG4_REG,
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GPIO_CFG4_REG, GPIO_CFG4_REG,
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/* GPIO 16 - 23 on the first strange EXTENDED register */
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EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
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EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
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EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
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/* GPIO 24 - 27 on the second strange EXTENDED register */
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EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG,
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EXTENDED_GPIO2_REG,
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};
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/* Maps 'basic' pins to relative offset from 0 per register */
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static int MSP_GPIO_OFFSET[] = {
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/* GPIO 0 and 1 on the first register */
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0, 0,
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/* GPIO 2, 3, 4, and 5 on the second register */
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2, 2, 2, 2,
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/* GPIO 6, 7, 8, and 9 on the third register */
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6, 6, 6, 6,
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/* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */
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10, 10, 10, 10, 10, 10,
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};
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/* Maps MODE to allowed pin mask */
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static unsigned int MSP_GPIO_MODE_ALLOWED[] = {
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0xffffffff, /* Mode 0 - INPUT */
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0x00000, /* Mode 1 - INTERRUPT */
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0x00030, /* Mode 2 - UART_INPUT (GPIO 4, 5)*/
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0, 0, 0, 0, 0, /* Modes 3, 4, 5, 6, and 7 are reserved */
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0xffffffff, /* Mode 8 - OUTPUT */
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0x0000f, /* Mode 9 - UART_OUTPUT/
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PERF_TIMERA (GPIO 0, 1, 2, 3) */
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0x00003, /* Mode a - PERF_TIMERB (GPIO 0, 1) */
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0x00000, /* Mode b - Not really a mode! */
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};
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/* -- Bit masks -- */
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/* This gives you the 'register relative offset gpio' number */
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#define OFFSET_GPIO_NUMBER(gpio) (gpio - MSP_GPIO_OFFSET[gpio])
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/* These take the 'register relative offset gpio' number */
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#define BASIC_DATA_REG_MASK(ogpio) (1 << ogpio)
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#define BASIC_MODE_REG_VALUE(mode, ogpio) \
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(mode << BASIC_MODE_REG_SHIFT(ogpio))
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#define BASIC_MODE_REG_MASK(ogpio) \
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BASIC_MODE_REG_VALUE(0xf, ogpio)
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#define BASIC_MODE_REG_SHIFT(ogpio) (ogpio * 4)
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#define BASIC_MODE_REG_FROM_REG(data, ogpio) \
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((data & BASIC_MODE_REG_MASK(ogpio)) >> BASIC_MODE_REG_SHIFT(ogpio))
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/* These take the actual GPIO number (0 through 15) */
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#define BASIC_DATA_MASK(gpio) \
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BASIC_DATA_REG_MASK(OFFSET_GPIO_NUMBER(gpio))
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#define BASIC_MODE_MASK(gpio) \
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BASIC_MODE_REG_MASK(OFFSET_GPIO_NUMBER(gpio))
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#define BASIC_MODE(mode, gpio) \
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BASIC_MODE_REG_VALUE(mode, OFFSET_GPIO_NUMBER(gpio))
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#define BASIC_MODE_SHIFT(gpio) \
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BASIC_MODE_REG_SHIFT(OFFSET_GPIO_NUMBER(gpio))
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#define BASIC_MODE_FROM_REG(data, gpio) \
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BASIC_MODE_REG_FROM_REG(data, OFFSET_GPIO_NUMBER(gpio))
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/*
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* Each extended GPIO register is 32 bits long and is responsible for up to
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* eight GPIOs. The least significant 16 bits contain the set and clear bit
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* pair for each of the GPIOs. The most significant 16 bits contain the
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* disable and enable bit pair for each of the GPIOs. For example, the
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* extended GPIO reg for GPIOs 16-23 is as follows:
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*
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* 31: GPIO23_DISABLE
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* ...
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* 19: GPIO17_DISABLE
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* 18: GPIO17_ENABLE
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* 17: GPIO16_DISABLE
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* 16: GPIO16_ENABLE
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* ...
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* 3: GPIO17_SET
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* 2: GPIO17_CLEAR
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* 1: GPIO16_SET
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* 0: GPIO16_CLEAR
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*/
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/* This gives the 'register relative offset gpio' number */
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#define EXTENDED_OFFSET_GPIO(gpio) (gpio < 24 ? gpio - 16 : gpio - 24)
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/* These take the 'register relative offset gpio' number */
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#define EXTENDED_REG_DISABLE(ogpio) (0x2 << ((ogpio * 2) + 16))
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#define EXTENDED_REG_ENABLE(ogpio) (0x1 << ((ogpio * 2) + 16))
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#define EXTENDED_REG_SET(ogpio) (0x2 << (ogpio * 2))
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#define EXTENDED_REG_CLR(ogpio) (0x1 << (ogpio * 2))
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/* These take the actual GPIO number (16 through 27) */
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#define EXTENDED_DISABLE(gpio) \
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EXTENDED_REG_DISABLE(EXTENDED_OFFSET_GPIO(gpio))
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#define EXTENDED_ENABLE(gpio) \
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EXTENDED_REG_ENABLE(EXTENDED_OFFSET_GPIO(gpio))
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#define EXTENDED_SET(gpio) \
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EXTENDED_REG_SET(EXTENDED_OFFSET_GPIO(gpio))
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#define EXTENDED_CLR(gpio) \
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EXTENDED_REG_CLR(EXTENDED_OFFSET_GPIO(gpio))
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#define EXTENDED_FULL_MASK (0xffffffff)
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/* -- API inline-functions -- */
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/*
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* Gets the current value of the specified pin
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*/
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static inline enum msp_gpio_data msp_gpio_pin_get(unsigned int gpio)
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{
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u32 pinhi_mask = 0, pinhi_mask2 = 0;
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if (gpio >= MSP_NUM_GPIOS)
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return MSP_GPIO_NONE;
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if (gpio < 16) {
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pinhi_mask = BASIC_DATA_MASK(gpio);
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} else {
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/*
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* Two cases are possible with the EXTENDED register:
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* - In output mode (ENABLED flag set), check the CLR bit
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* - In input mode (ENABLED flag not set), check the SET bit
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*/
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pinhi_mask = EXTENDED_ENABLE(gpio) | EXTENDED_CLR(gpio);
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pinhi_mask2 = EXTENDED_SET(gpio);
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}
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if (((*MSP_GPIO_DATA_REGISTER[gpio] & pinhi_mask) == pinhi_mask) ||
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(*MSP_GPIO_DATA_REGISTER[gpio] & pinhi_mask2))
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return MSP_GPIO_HI;
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else
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return MSP_GPIO_LO;
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}
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/* Sets the specified pin to the specified value */
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static inline void msp_gpio_pin_set(enum msp_gpio_data data, unsigned int gpio)
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{
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if (gpio >= MSP_NUM_GPIOS)
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return;
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if (gpio < 16) {
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if (data == MSP_GPIO_TOGGLE)
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toggle_reg32(MSP_GPIO_DATA_REGISTER[gpio],
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BASIC_DATA_MASK(gpio));
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else if (data == MSP_GPIO_HI)
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set_reg32(MSP_GPIO_DATA_REGISTER[gpio],
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BASIC_DATA_MASK(gpio));
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else
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clear_reg32(MSP_GPIO_DATA_REGISTER[gpio],
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BASIC_DATA_MASK(gpio));
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} else {
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if (data == MSP_GPIO_TOGGLE) {
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/* Special ugly case:
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* We have to read the CLR bit.
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* If set, we write the CLR bit.
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* If not, we write the SET bit.
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*/
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u32 tmpdata;
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custom_read_reg32(MSP_GPIO_DATA_REGISTER[gpio],
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tmpdata);
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if (tmpdata & EXTENDED_CLR(gpio))
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tmpdata = EXTENDED_CLR(gpio);
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else
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tmpdata = EXTENDED_SET(gpio);
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custom_write_reg32(MSP_GPIO_DATA_REGISTER[gpio],
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tmpdata);
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} else {
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u32 newdata;
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if (data == MSP_GPIO_HI)
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newdata = EXTENDED_SET(gpio);
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else
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newdata = EXTENDED_CLR(gpio);
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set_value_reg32(MSP_GPIO_DATA_REGISTER[gpio],
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EXTENDED_FULL_MASK, newdata);
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}
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}
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}
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/* Sets the specified pin to the specified value */
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static inline void msp_gpio_pin_hi(unsigned int gpio)
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{
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msp_gpio_pin_set(MSP_GPIO_HI, gpio);
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}
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/* Sets the specified pin to the specified value */
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static inline void msp_gpio_pin_lo(unsigned int gpio)
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{
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msp_gpio_pin_set(MSP_GPIO_LO, gpio);
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}
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/* Sets the specified pin to the opposite value */
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static inline void msp_gpio_pin_toggle(unsigned int gpio)
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{
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msp_gpio_pin_set(MSP_GPIO_TOGGLE, gpio);
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}
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/* Gets the mode of the specified pin */
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static inline enum msp_gpio_mode msp_gpio_pin_get_mode(unsigned int gpio)
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{
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enum msp_gpio_mode retval = MSP_GPIO_UNKNOWN;
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uint32_t data;
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if (gpio >= MSP_NUM_GPIOS)
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return retval;
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data = *MSP_GPIO_MODE_REGISTER[gpio];
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if (gpio < 16) {
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retval = BASIC_MODE_FROM_REG(data, gpio);
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} else {
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/* Extended pins can only be either INPUT or OUTPUT */
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if (data & EXTENDED_ENABLE(gpio))
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retval = MSP_GPIO_OUTPUT;
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else
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retval = MSP_GPIO_INPUT;
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}
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return retval;
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}
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/*
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* Sets the specified mode on the requested pin
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* Returns 0 on success, or -1 if that mode is not allowed on this pin
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*/
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static inline int msp_gpio_pin_mode(enum msp_gpio_mode mode, unsigned int gpio)
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{
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u32 modemask, newmode;
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if ((1 << gpio) & ~MSP_GPIO_MODE_ALLOWED[mode])
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return -1;
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if (gpio >= MSP_NUM_GPIOS)
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return -1;
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if (gpio < 16) {
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modemask = BASIC_MODE_MASK(gpio);
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newmode = BASIC_MODE(mode, gpio);
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} else {
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modemask = EXTENDED_FULL_MASK;
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if (mode == MSP_GPIO_INPUT)
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newmode = EXTENDED_DISABLE(gpio);
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else
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newmode = EXTENDED_ENABLE(gpio);
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}
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/* Do the set atomically */
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set_value_reg32(MSP_GPIO_MODE_REGISTER[gpio], modemask, newmode);
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return 0;
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}
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#endif /* __MSP_GPIO_MACROS_H__ */
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