122 lines
3.6 KiB
C
122 lines
3.6 KiB
C
/*
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* Based on arch/arm/include/asm/pmu.h
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*
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* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PMU_H
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#define __ASM_PMU_H
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#ifdef CONFIG_HW_PERF_EVENTS
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enum arm_pmu_state {
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ARM_PMU_STATE_OFF = 0,
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ARM_PMU_STATE_GOING_DOWN,
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ARM_PMU_STATE_RUNNING,
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};
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/* The events for a given PMU register set. */
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struct pmu_hw_events {
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/*
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* The events that are active on the PMU for the given index.
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*/
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struct perf_event **events;
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/*
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* A 1 bit for an index indicates that the counter is being used for
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* an event. A 0 means that the counter can be used.
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*/
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unsigned long *used_mask;
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u32 *from_idle;
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/*
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* Hardware lock to serialize accesses to PMU registers. Needed for the
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* read/modify/write sequences.
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*/
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raw_spinlock_t pmu_lock;
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};
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struct arm_pmu {
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struct pmu pmu;
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cpumask_t active_irqs;
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const char *name;
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irqreturn_t (*handle_irq)(int irq_num, void *dev);
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void (*enable)(struct hw_perf_event *evt, int idx);
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void (*disable)(struct hw_perf_event *evt, int idx);
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int (*get_event_idx)(struct pmu_hw_events *hw_events,
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struct hw_perf_event *hwc);
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int (*set_event_filter)(struct hw_perf_event *evt,
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struct perf_event_attr *attr);
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u32 (*read_counter)(int idx);
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void (*write_counter)(int idx, u32 val);
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void (*start)(void);
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void (*stop)(void);
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void (*reset)(void *);
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int (*request_irq)(struct arm_pmu *,
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irq_handler_t handler);
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void (*free_irq)(struct arm_pmu *);
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int (*map_event)(struct perf_event *event);
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int num_events;
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int pmu_state;
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int percpu_irq;
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atomic_t active_events;
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struct mutex reserve_mutex;
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u64 max_period;
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struct platform_device *plat_device;
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struct pmu_hw_events *(*get_hw_events)(void);
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void (*save_pm_registers)(void *hcpu);
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void (*restore_pm_registers)(void *hcpu);
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int (*check_event)(
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struct arm_pmu *armpmu,
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struct hw_perf_event *hwc);
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};
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#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
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extern const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX];
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extern const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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int map_cpu_event(struct perf_event *event,
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const unsigned (*event_map)[PERF_COUNT_HW_MAX],
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const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX],
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u32 raw_event_mask);
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int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
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u64 armpmu_event_update(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx);
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int armpmu_event_set_period(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx);
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int armv8pmu_enable_intens(int idx);
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int armv8pmu_disable_intens(int idx);
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int armv8pmu_enable_counter(int idx);
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int armv8pmu_disable_counter(int idx);
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u32 armv8pmu_getreset_flags(void);
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void armv8pmu_pmcr_write(u32 val);
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void armv8pmu_write_evtype(int idx, u32 val);
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int kryo_pmu_init(struct arm_pmu *cpu_pmu);
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#endif /* CONFIG_HW_PERF_EVENTS */
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#endif /* __ASM_PMU_H */
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