133 lines
3.0 KiB
C
133 lines
3.0 KiB
C
/*
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* arch/arm64/include/asm/arch_timer.h
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARCH_TIMER_H
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#define __ASM_ARCH_TIMER_H
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#include <asm/barrier.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <clocksource/arm_arch_timer.h>
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/*
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* These register accessors are marked inline so the compiler can
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* nicely work out which register we want, and chuck away the rest of
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* the code.
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*/
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static __always_inline
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void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("msr cntp_ctl_el0, %0" : : "r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("msr cntp_tval_el0, %0" : : "r" (val));
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break;
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("msr cntv_ctl_el0, %0" : : "r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("msr cntv_tval_el0, %0" : : "r" (val));
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break;
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}
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}
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isb();
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}
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static __always_inline
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u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
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{
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u32 val;
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mrs %0, cntp_ctl_el0" : "=r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
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break;
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mrs %0, cntv_ctl_el0" : "=r" (val));
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break;
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case ARCH_TIMER_REG_TVAL:
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asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
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break;
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}
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}
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return val;
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}
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static inline u32 arch_timer_get_cntfrq(void)
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{
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u32 val;
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asm volatile("mrs %0, cntfrq_el0" : "=r" (val));
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return val;
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}
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static inline u32 arch_timer_get_cntkctl(void)
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{
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u32 cntkctl;
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asm volatile("mrs %0, cntkctl_el1" : "=r" (cntkctl));
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return cntkctl;
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}
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static inline void arch_timer_set_cntkctl(u32 cntkctl)
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{
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asm volatile("msr cntkctl_el1, %0" : : "r" (cntkctl));
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}
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static inline u64 arch_counter_get_cntvct_cp15(void)
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{
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u64 cval;
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isb();
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asm volatile("mrs %0, cntvct_el0" : "=r" (cval));
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return cval;
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}
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static inline u64 arch_counter_get_cntpct_cp15(void)
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{
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u64 cval;
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isb();
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asm volatile("mrs %0, cntpct_el0" : "=r" (cval));
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return cval;
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}
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static inline int arch_timer_arch_init(void)
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{
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return 0;
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}
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#endif
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