281 lines
8.7 KiB
C
281 lines
8.7 KiB
C
/*
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* linux/arch/arm/mach-omap2/clock.h
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*
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* Copyright (C) 2005-2009 Texas Instruments, Inc.
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* Copyright (C) 2004-2011 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/ti.h>
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struct omap_clk {
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u16 cpu;
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struct clk_lookup lk;
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};
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#define CLK(dev, con, ck) \
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{ \
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.lk = { \
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.dev_id = dev, \
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.con_id = con, \
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.clk = ck, \
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}, \
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}
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struct clockdomain;
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#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
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static struct clk _name = { \
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.name = #_name, \
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.hw = &_name##_hw.hw, \
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.parent_names = _parent_array_name, \
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.num_parents = ARRAY_SIZE(_parent_array_name), \
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.ops = &_clkops_name, \
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};
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#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
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_clkops_name, _flags) \
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static struct clk _name = { \
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.name = #_name, \
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.hw = &_name##_hw.hw, \
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.parent_names = _parent_array_name, \
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.num_parents = ARRAY_SIZE(_parent_array_name), \
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.ops = &_clkops_name, \
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.flags = _flags, \
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};
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#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
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static struct clk_hw_omap _name##_hw = { \
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.hw = { \
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.clk = &_name, \
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}, \
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.clkdm_name = _clkdm_name, \
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};
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#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \
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_clksel_reg, _clksel_mask, \
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_parent_names, _ops) \
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static struct clk _name; \
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static struct clk_hw_omap _name##_hw = { \
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.hw = { \
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.clk = &_name, \
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}, \
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.clksel = _clksel, \
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.clksel_reg = _clksel_reg, \
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.clksel_mask = _clksel_mask, \
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.clkdm_name = _clkdm_name, \
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}; \
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DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
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#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \
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_clksel_reg, _clksel_mask, \
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_enable_reg, _enable_bit, \
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_hwops, _parent_names, _ops) \
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static struct clk _name; \
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static struct clk_hw_omap _name##_hw = { \
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.hw = { \
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.clk = &_name, \
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}, \
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.ops = _hwops, \
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.enable_reg = _enable_reg, \
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.enable_bit = _enable_bit, \
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.clksel = _clksel, \
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.clksel_reg = _clksel_reg, \
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.clksel_mask = _clksel_mask, \
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.clkdm_name = _clkdm_name, \
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}; \
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DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
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/* struct clksel_rate.flags possibilities */
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#define RATE_IN_242X (1 << 0)
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#define RATE_IN_243X (1 << 1)
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#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
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#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
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#define RATE_IN_36XX (1 << 4)
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#define RATE_IN_4430 (1 << 5)
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#define RATE_IN_TI816X (1 << 6)
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#define RATE_IN_4460 (1 << 7)
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#define RATE_IN_AM33XX (1 << 8)
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#define RATE_IN_TI814X (1 << 9)
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#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
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#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
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#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
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#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
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/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
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#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
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/**
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* struct clksel_rate - register bitfield values corresponding to clk divisors
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* @val: register bitfield value (shifted to bit 0)
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* @div: clock divisor corresponding to @val
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* @flags: (see "struct clksel_rate.flags possibilities" above)
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*
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* @val should match the value of a read from struct clk.clksel_reg
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* AND'ed with struct clk.clksel_mask, shifted right to bit 0.
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*
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* @div is the divisor that should be applied to the parent clock's rate
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* to produce the current clock's rate.
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*/
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struct clksel_rate {
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u32 val;
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u8 div;
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u16 flags;
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};
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/**
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* struct clksel - available parent clocks, and a pointer to their divisors
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* @parent: struct clk * to a possible parent clock
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* @rates: available divisors for this parent clock
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*
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* A struct clksel is always associated with one or more struct clks
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* and one or more struct clksel_rates.
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*/
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struct clksel {
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struct clk *parent;
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const struct clksel_rate *rates;
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};
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/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
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#define CORE_CLK_SRC_32K 0x0
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#define CORE_CLK_SRC_DPLL 0x1
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#define CORE_CLK_SRC_DPLL_X2 0x2
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/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
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#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
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#define OMAP2XXX_EN_DPLL_LOCKED 0x3
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/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
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#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP3XXX_EN_DPLL_LOCKED 0x7
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/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
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#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
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#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP4XXX_EN_DPLL_LOCKED 0x7
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u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
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void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
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void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
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int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
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void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
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void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
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void __init omap2_clk_disable_clkdm_control(void);
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/* clkt_clksel.c public functions */
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u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
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unsigned long target_rate,
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u32 *new_div);
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u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
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unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
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long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
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unsigned long *parent_rate);
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int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
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/* clkt_iclk.c public functions */
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extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
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extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
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unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
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void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
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void __iomem **other_reg,
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u8 *other_bit);
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void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
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void __iomem **idlest_reg,
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u8 *idlest_bit, u8 *idlest_val);
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int omap2_clk_enable_autoidle_all(void);
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int omap2_clk_allow_idle(struct clk *clk);
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int omap2_clk_deny_idle(struct clk *clk);
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int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
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void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
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const char *core_ck_name,
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const char *mpu_ck_name);
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u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
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void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
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extern u16 cpu_mask;
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/*
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* Clock features setup. Used instead of CPU type checks.
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*/
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struct ti_clk_features {
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u32 flags;
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long fint_min;
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long fint_max;
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long fint_band1_max;
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long fint_band2_min;
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u8 dpll_bypass_vals;
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u8 cm_idlest_val;
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};
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#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0)
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extern struct ti_clk_features ti_clk_features;
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extern const struct clkops clkops_omap2_dflt_wait;
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extern const struct clkops clkops_dummy;
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extern const struct clkops clkops_omap2_dflt;
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extern struct clk_functions omap2_clk_functions;
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extern const struct clksel_rate gpt_32k_rates[];
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extern const struct clksel_rate gpt_sys_rates[];
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extern const struct clksel_rate gfx_l3_rates[];
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extern const struct clksel_rate dsp_ick_rates[];
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extern struct clk dummy_ck;
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extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
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extern const struct clk_hw_omap_ops clkhwops_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
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extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
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extern const struct clk_hw_omap_ops clkhwops_apll54;
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extern const struct clk_hw_omap_ops clkhwops_apll96;
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/* clksel_rate blocks shared between OMAP44xx and AM33xx */
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extern const struct clksel_rate div_1_0_rates[];
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extern const struct clksel_rate div3_1to4_rates[];
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extern const struct clksel_rate div_1_1_rates[];
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extern const struct clksel_rate div_1_2_rates[];
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extern const struct clksel_rate div_1_3_rates[];
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extern const struct clksel_rate div_1_4_rates[];
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extern const struct clksel_rate div31_1to31_rates[];
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extern void __iomem *clk_memmaps[];
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extern int am33xx_clk_init(void);
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extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
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extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
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extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
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void __init ti_clk_init_features(void);
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#endif
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