403 lines
11 KiB
C
403 lines
11 KiB
C
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/mm.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/opcodes.h>
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#include <trace/events/kvm.h>
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#include "trace.h"
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#define VCPU_NR_MODES 6
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#define VCPU_REG_OFFSET_USR 0
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#define VCPU_REG_OFFSET_FIQ 1
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#define VCPU_REG_OFFSET_IRQ 2
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#define VCPU_REG_OFFSET_SVC 3
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#define VCPU_REG_OFFSET_ABT 4
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#define VCPU_REG_OFFSET_UND 5
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#define REG_OFFSET(_reg) \
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(offsetof(struct kvm_regs, _reg) / sizeof(u32))
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#define USR_REG_OFFSET(_num) REG_OFFSET(usr_regs.uregs[_num])
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static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = {
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/* USR/SYS Registers */
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[VCPU_REG_OFFSET_USR] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14),
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},
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/* FIQ Registers */
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[VCPU_REG_OFFSET_FIQ] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7),
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REG_OFFSET(fiq_regs[0]), /* r8 */
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REG_OFFSET(fiq_regs[1]), /* r9 */
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REG_OFFSET(fiq_regs[2]), /* r10 */
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REG_OFFSET(fiq_regs[3]), /* r11 */
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REG_OFFSET(fiq_regs[4]), /* r12 */
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REG_OFFSET(fiq_regs[5]), /* r13 */
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REG_OFFSET(fiq_regs[6]), /* r14 */
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},
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/* IRQ Registers */
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[VCPU_REG_OFFSET_IRQ] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(irq_regs[0]), /* r13 */
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REG_OFFSET(irq_regs[1]), /* r14 */
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},
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/* SVC Registers */
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[VCPU_REG_OFFSET_SVC] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(svc_regs[0]), /* r13 */
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REG_OFFSET(svc_regs[1]), /* r14 */
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},
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/* ABT Registers */
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[VCPU_REG_OFFSET_ABT] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(abt_regs[0]), /* r13 */
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REG_OFFSET(abt_regs[1]), /* r14 */
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},
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/* UND Registers */
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[VCPU_REG_OFFSET_UND] = {
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(und_regs[0]), /* r13 */
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REG_OFFSET(und_regs[1]), /* r14 */
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},
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};
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/*
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* Return a pointer to the register number valid in the current mode of
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* the virtual CPU.
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*/
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unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
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{
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unsigned long *reg_array = (unsigned long *)&vcpu->arch.regs;
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unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
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switch (mode) {
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case USR_MODE...SVC_MODE:
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mode &= ~MODE32_BIT; /* 0 ... 3 */
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break;
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case ABT_MODE:
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mode = VCPU_REG_OFFSET_ABT;
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break;
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case UND_MODE:
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mode = VCPU_REG_OFFSET_UND;
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break;
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case SYSTEM_MODE:
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mode = VCPU_REG_OFFSET_USR;
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break;
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default:
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BUG();
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}
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return reg_array + vcpu_reg_offsets[mode][reg_num];
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}
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/*
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* Return the SPSR for the current mode of the virtual CPU.
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*/
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unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu)
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{
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unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
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switch (mode) {
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case SVC_MODE:
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return &vcpu->arch.regs.KVM_ARM_SVC_spsr;
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case ABT_MODE:
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return &vcpu->arch.regs.KVM_ARM_ABT_spsr;
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case UND_MODE:
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return &vcpu->arch.regs.KVM_ARM_UND_spsr;
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case IRQ_MODE:
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return &vcpu->arch.regs.KVM_ARM_IRQ_spsr;
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case FIQ_MODE:
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return &vcpu->arch.regs.KVM_ARM_FIQ_spsr;
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default:
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BUG();
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}
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}
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/*
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* A conditional instruction is allowed to trap, even though it
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* wouldn't be executed. So let's re-implement the hardware, in
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* software!
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*/
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bool kvm_condition_valid(struct kvm_vcpu *vcpu)
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{
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unsigned long cpsr, cond, insn;
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/*
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* Exception Code 0 can only happen if we set HCR.TGE to 1, to
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* catch undefined instructions, and then we won't get past
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* the arm_exit_handlers test anyway.
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*/
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BUG_ON(!kvm_vcpu_trap_get_class(vcpu));
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/* Top two bits non-zero? Unconditional. */
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if (kvm_vcpu_get_hsr(vcpu) >> 30)
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return true;
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cpsr = *vcpu_cpsr(vcpu);
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/* Is condition field valid? */
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if ((kvm_vcpu_get_hsr(vcpu) & HSR_CV) >> HSR_CV_SHIFT)
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cond = (kvm_vcpu_get_hsr(vcpu) & HSR_COND) >> HSR_COND_SHIFT;
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else {
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/* This can happen in Thumb mode: examine IT state. */
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unsigned long it;
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it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
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/* it == 0 => unconditional. */
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if (it == 0)
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return true;
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/* The cond for this insn works out as the top 4 bits. */
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cond = (it >> 4);
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}
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/* Shift makes it look like an ARM-mode instruction */
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insn = cond << 28;
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return arm_check_condition(insn, cpsr) != ARM_OPCODE_CONDTEST_FAIL;
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}
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/**
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* adjust_itstate - adjust ITSTATE when emulating instructions in IT-block
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* @vcpu: The VCPU pointer
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*
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* When exceptions occur while instructions are executed in Thumb IF-THEN
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* blocks, the ITSTATE field of the CPSR is not advanved (updated), so we have
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* to do this little bit of work manually. The fields map like this:
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*
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* IT[7:0] -> CPSR[26:25],CPSR[15:10]
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*/
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static void kvm_adjust_itstate(struct kvm_vcpu *vcpu)
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{
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unsigned long itbits, cond;
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unsigned long cpsr = *vcpu_cpsr(vcpu);
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bool is_arm = !(cpsr & PSR_T_BIT);
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BUG_ON(is_arm && (cpsr & PSR_IT_MASK));
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if (!(cpsr & PSR_IT_MASK))
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return;
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cond = (cpsr & 0xe000) >> 13;
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itbits = (cpsr & 0x1c00) >> (10 - 2);
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itbits |= (cpsr & (0x3 << 25)) >> 25;
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/* Perform ITAdvance (see page A-52 in ARM DDI 0406C) */
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if ((itbits & 0x7) == 0)
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itbits = cond = 0;
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else
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itbits = (itbits << 1) & 0x1f;
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cpsr &= ~PSR_IT_MASK;
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cpsr |= cond << 13;
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cpsr |= (itbits & 0x1c) << (10 - 2);
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cpsr |= (itbits & 0x3) << 25;
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*vcpu_cpsr(vcpu) = cpsr;
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}
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/**
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* kvm_skip_instr - skip a trapped instruction and proceed to the next
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* @vcpu: The vcpu pointer
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*/
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void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
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{
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bool is_thumb;
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is_thumb = !!(*vcpu_cpsr(vcpu) & PSR_T_BIT);
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if (is_thumb && !is_wide_instr)
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*vcpu_pc(vcpu) += 2;
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else
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*vcpu_pc(vcpu) += 4;
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kvm_adjust_itstate(vcpu);
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}
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/******************************************************************************
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* Inject exceptions into the guest
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*/
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static u32 exc_vector_base(struct kvm_vcpu *vcpu)
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{
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u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
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u32 vbar = vcpu->arch.cp15[c12_VBAR];
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if (sctlr & SCTLR_V)
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return 0xffff0000;
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else /* always have security exceptions */
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return vbar;
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}
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/**
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* kvm_inject_undefined - inject an undefined exception into the guest
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* @vcpu: The VCPU to receive the undefined exception
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*
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* Modelled after TakeUndefInstrException() pseudocode.
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*/
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void kvm_inject_undefined(struct kvm_vcpu *vcpu)
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{
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unsigned long new_lr_value;
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unsigned long new_spsr_value;
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unsigned long cpsr = *vcpu_cpsr(vcpu);
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u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
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bool is_thumb = (cpsr & PSR_T_BIT);
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u32 vect_offset = 4;
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u32 return_offset = (is_thumb) ? 2 : 4;
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new_spsr_value = cpsr;
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new_lr_value = *vcpu_pc(vcpu) - return_offset;
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*vcpu_cpsr(vcpu) = (cpsr & ~MODE_MASK) | UND_MODE;
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*vcpu_cpsr(vcpu) |= PSR_I_BIT;
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*vcpu_cpsr(vcpu) &= ~(PSR_IT_MASK | PSR_J_BIT | PSR_E_BIT | PSR_T_BIT);
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if (sctlr & SCTLR_TE)
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*vcpu_cpsr(vcpu) |= PSR_T_BIT;
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if (sctlr & SCTLR_EE)
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*vcpu_cpsr(vcpu) |= PSR_E_BIT;
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/* Note: These now point to UND banked copies */
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*vcpu_spsr(vcpu) = cpsr;
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*vcpu_reg(vcpu, 14) = new_lr_value;
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/* Branch to exception vector */
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*vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset;
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}
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/*
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* Modelled after TakeDataAbortException() and TakePrefetchAbortException
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* pseudocode.
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*/
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static void inject_abt(struct kvm_vcpu *vcpu, bool is_pabt, unsigned long addr)
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{
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unsigned long new_lr_value;
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unsigned long new_spsr_value;
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unsigned long cpsr = *vcpu_cpsr(vcpu);
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u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
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bool is_thumb = (cpsr & PSR_T_BIT);
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u32 vect_offset;
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u32 return_offset = (is_thumb) ? 4 : 0;
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bool is_lpae;
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new_spsr_value = cpsr;
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new_lr_value = *vcpu_pc(vcpu) + return_offset;
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*vcpu_cpsr(vcpu) = (cpsr & ~MODE_MASK) | ABT_MODE;
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*vcpu_cpsr(vcpu) |= PSR_I_BIT | PSR_A_BIT;
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*vcpu_cpsr(vcpu) &= ~(PSR_IT_MASK | PSR_J_BIT | PSR_E_BIT | PSR_T_BIT);
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if (sctlr & SCTLR_TE)
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*vcpu_cpsr(vcpu) |= PSR_T_BIT;
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if (sctlr & SCTLR_EE)
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*vcpu_cpsr(vcpu) |= PSR_E_BIT;
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/* Note: These now point to ABT banked copies */
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*vcpu_spsr(vcpu) = cpsr;
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*vcpu_reg(vcpu, 14) = new_lr_value;
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if (is_pabt)
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vect_offset = 12;
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else
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vect_offset = 16;
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/* Branch to exception vector */
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*vcpu_pc(vcpu) = exc_vector_base(vcpu) + vect_offset;
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if (is_pabt) {
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/* Set IFAR and IFSR */
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vcpu->arch.cp15[c6_IFAR] = addr;
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is_lpae = (vcpu->arch.cp15[c2_TTBCR] >> 31);
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/* Always give debug fault for now - should give guest a clue */
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if (is_lpae)
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vcpu->arch.cp15[c5_IFSR] = 1 << 9 | 0x22;
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else
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vcpu->arch.cp15[c5_IFSR] = 2;
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} else { /* !iabt */
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/* Set DFAR and DFSR */
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vcpu->arch.cp15[c6_DFAR] = addr;
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is_lpae = (vcpu->arch.cp15[c2_TTBCR] >> 31);
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/* Always give debug fault for now - should give guest a clue */
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if (is_lpae)
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vcpu->arch.cp15[c5_DFSR] = 1 << 9 | 0x22;
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else
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vcpu->arch.cp15[c5_DFSR] = 2;
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}
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}
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/**
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* kvm_inject_dabt - inject a data abort into the guest
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* @vcpu: The VCPU to receive the undefined exception
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* @addr: The address to report in the DFAR
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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inject_abt(vcpu, false, addr);
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}
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/**
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* kvm_inject_pabt - inject a prefetch abort into the guest
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* @vcpu: The VCPU to receive the undefined exception
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* @addr: The address to report in the DFAR
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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inject_abt(vcpu, true, addr);
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}
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