163 lines
5.4 KiB
Plaintext
163 lines
5.4 KiB
Plaintext
/*
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* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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qcom,msm-cam@1800000{
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compatible = "qcom,msm-cam";
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};
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qcom,csiphy@1b0ac00 {
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cell-index = <0>;
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compatible = "qcom,csiphy-v3.1", "qcom,csiphy";
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reg = <0x1b0ac00 0x200>,
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<0x1b00030 0x4>;
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reg-names = "csiphy", "csiphy_clk_mux";
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interrupts = <0 78 0>;
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interrupt-names = "csiphy";
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clocks = <&clock_gcc clk_gcc_camss_top_ahb_clk>,
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<&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
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<&clock_gcc clk_csi0phytimer_clk_src>,
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<&clock_gcc clk_gcc_camss_csi0phytimer_clk>,
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<&clock_gcc clk_camss_top_ahb_clk_src>,
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<&clock_gcc clk_gcc_camss_csi0phy_clk>,
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<&clock_gcc clk_gcc_camss_csi1phy_clk>,
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<&clock_gcc clk_gcc_camss_ahb_clk>;
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clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",
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"csiphy_timer_src_clk", "csiphy_timer_clk",
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"camss_ahb_src", "csi0_phy_clk", "csi1_phy_clk",
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"camss_ahb_clk";
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qcom,clock-rates = <0 0 200000000 0 0 0 0 0>;
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};
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qcom,csid@1b08000 {
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cell-index = <0>;
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compatible = "qcom,csid-v3.1", "qcom,csid";
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reg = <0x1b08000 0x100>;
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reg-names = "csid";
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interrupts = <0 49 0>;
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interrupt-names = "csid";
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qcom,csi-vdd-voltage = <1200000>;
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qcom,mipi-csi-vdd-supply = <&pm8916_l2>;
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clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
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<&clock_gcc clk_gcc_camss_top_ahb_clk>,
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<&clock_gcc clk_gcc_camss_csi0_ahb_clk>,
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<&clock_gcc clk_csi0_clk_src>,
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<&clock_gcc clk_gcc_camss_csi0_clk>,
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<&clock_gcc clk_gcc_camss_csi0pix_clk>,
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<&clock_gcc clk_gcc_camss_csi0rdi_clk>,
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<&clock_gcc clk_gcc_camss_ahb_clk>;
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clock-names = "ispif_ahb_clk", "camss_top_ahb_clk",
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"csi_ahb_clk", "csi_src_clk",
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"csi_clk", "csi_pix_clk",
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"csi_rdi_clk", "camss_ahb_clk";
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qcom,clock-rates = <40000000 0 0 200000000 0 0 0 0>;
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};
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qcom,csid@1b08400 {
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cell-index = <1>;
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compatible = "qcom,csid-v3.1", "qcom,csid";
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reg = <0x1b08400 0x100>;
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reg-names = "csid";
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interrupts = <0 50 0>;
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interrupt-names = "csid";
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qcom,csi-vdd-voltage = <1200000>;
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qcom,mipi-csi-vdd-supply = <&pm8916_l2>;
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clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
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<&clock_gcc clk_gcc_camss_top_ahb_clk>,
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<&clock_gcc clk_gcc_camss_csi1_ahb_clk>,
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<&clock_gcc clk_csi1_clk_src>,
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<&clock_gcc clk_gcc_camss_csi1_clk>,
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<&clock_gcc clk_gcc_camss_csi1pix_clk>,
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<&clock_gcc clk_gcc_camss_csi1rdi_clk>,
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<&clock_gcc clk_gcc_camss_ahb_clk>,
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<&clock_gcc clk_gcc_camss_csi1phy_clk>;
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clock-names = "ispif_ahb_clk", "camss_top_ahb_clk",
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"csi_ahb_clk", "csi_src_clk",
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"csi_clk", "csi_pix_clk",
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"csi_rdi_clk", "camss_ahb_clk", "camss_csi1_phy";
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qcom,clock-rates = <40000000 0 0 200000000 0 0 0 0 0>;
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};
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qcom,ispif@1b0a000 {
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cell-index = <0>;
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compatible = "qcom,ispif";
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reg = <0x1b0a000 0x500>,
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<0x1b00020 0x10>;
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reg-names = "ispif", "csi_clk_mux";
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interrupts = <0 51 0>;
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interrupt-names = "ispif";
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clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
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<&clock_gcc clk_gcc_camss_ahb_clk>,
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<&clock_gcc clk_csi0_clk_src>,
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<&clock_gcc clk_gcc_camss_csi0_clk>,
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<&clock_gcc clk_gcc_camss_csi0pix_clk>,
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<&clock_gcc clk_gcc_camss_csi0rdi_clk>,
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<&clock_gcc clk_csi1_clk_src>,
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<&clock_gcc clk_gcc_camss_csi1_clk>,
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<&clock_gcc clk_gcc_camss_csi1pix_clk>,
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<&clock_gcc clk_gcc_camss_csi1rdi_clk>,
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<&clock_gcc clk_vfe0_clk_src>,
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<&clock_gcc clk_gcc_camss_vfe0_clk>,
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<&clock_gcc clk_gcc_camss_csi_vfe0_clk>;
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clock-names = "ispif_ahb_clk","camss_ahb_clk",
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"csi0_src_clk", "csi0_clk",
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"csi0_pix_clk","csi0_rdi_clk", "csi1_src_clk",
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"csi1_clk", "csi1_pix_clk", "csi1_rdi_clk",
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"vfe0_clk_src", "camss_vfe_vfe0_clk",
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"camss_csi_vfe0_clk";
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qcom,clock-rates = <40000000 0 0 0 0 0 0 0 0 0 0 0 0>;
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};
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qcom,vfe@1b10000 {
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cell-index = <0>;
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compatible = "qcom,vfe32";
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reg = <0x1b10000 0x830>,
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<0x1b40000 0x200>;
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reg-names = "vfe", "vfe_vbif";
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interrupts = <0 52 0>;
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interrupt-names = "vfe";
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vdd-supply = <&gdsc_vfe>;
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clocks = <&clock_gcc clk_gcc_camss_ispif_ahb_clk>,
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<&clock_gcc clk_vfe0_clk_src>,
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<&clock_gcc clk_gcc_camss_vfe0_clk>,
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<&clock_gcc clk_gcc_camss_csi_vfe0_clk>,
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<&clock_gcc clk_gcc_camss_vfe_ahb_clk>,
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<&clock_gcc clk_gcc_camss_vfe_axi_clk>,
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<&clock_gcc clk_gcc_camss_ahb_clk>,
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<&clock_gcc clk_gcc_camss_top_ahb_clk>;
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clock-names = "camss_top_ahb_clk", "vfe_clk_src",
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"camss_vfe_vfe_clk", "camss_csi_vfe_clk", "iface_clk",
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"bus_clk", "camss_ahb_clk", "ispif_ahb_clk";
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qcom,clock-rates = <40000000 266670000 0 0 0 0 0 0>;
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qos-entries = <8>;
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qos-regs = <0x7BC 0x7C0 0x7C4 0x7C8 0x7CC 0x7D0
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0x7D4 0x798>;
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qos-settings = <0xAAA5AAA5 0xAAA5AAA5 0xAAA5AAA5
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0xAAA5AAA5 0xAAA5AAA5 0xAAA5AAA5
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0xAAA5AAA5 0x00010000>;
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vbif-entries = <1>;
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vbif-regs = <0x04>;
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vbif-settings = <0x1>;
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ds-entries = <15>;
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ds-regs = <0x7D8 0x7DC 0x7E0 0x7E4 0x7E8
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0x7EC 0x7F0 0x7F4 0x7F8 0x7FC 0x800
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0x804 0x808 0x80C 0x810>;
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ds-settings = <0xCCCC1111 0xCCCC1111 0xCCCC1111
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0xCCCC1111 0xCCCC1111 0xCCCC1111
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0xCCCC1111 0xCCCC1111 0xCCCC1111
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0xCCCC1111 0xCCCC1111 0xCCCC1111
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0xCCCC1111 0xCCCC1111 0x00000103>;
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};
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};
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