267 lines
9.8 KiB
Plaintext
267 lines
9.8 KiB
Plaintext
KVM-specific MSRs.
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Glauber Costa <glommer@redhat.com>, Red Hat Inc, 2010
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=====================================================
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KVM makes use of some custom MSRs to service some requests.
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Custom MSRs have a range reserved for them, that goes from
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0x4b564d00 to 0x4b564dff. There are MSRs outside this area,
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but they are deprecated and their use is discouraged.
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Custom MSR list
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--------
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The current supported Custom MSR list is:
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MSR_KVM_WALL_CLOCK_NEW: 0x4b564d00
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data: 4-byte alignment physical address of a memory area which must be
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in guest RAM. This memory is expected to hold a copy of the following
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structure:
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struct pvclock_wall_clock {
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u32 version;
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u32 sec;
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u32 nsec;
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} __attribute__((__packed__));
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whose data will be filled in by the hypervisor. The hypervisor is only
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guaranteed to update this data at the moment of MSR write.
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Users that want to reliably query this information more than once have
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to write more than once to this MSR. Fields have the following meanings:
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version: guest has to check version before and after grabbing
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time information and check that they are both equal and even.
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An odd version indicates an in-progress update.
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sec: number of seconds for wallclock at time of boot.
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nsec: number of nanoseconds for wallclock at time of boot.
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In order to get the current wallclock time, the system_time from
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MSR_KVM_SYSTEM_TIME_NEW needs to be added.
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Note that although MSRs are per-CPU entities, the effect of this
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particular MSR is global.
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Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
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leaf prior to usage.
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MSR_KVM_SYSTEM_TIME_NEW: 0x4b564d01
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data: 4-byte aligned physical address of a memory area which must be in
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guest RAM, plus an enable bit in bit 0. This memory is expected to hold
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a copy of the following structure:
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struct pvclock_vcpu_time_info {
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u32 version;
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u32 pad0;
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u64 tsc_timestamp;
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u64 system_time;
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u32 tsc_to_system_mul;
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s8 tsc_shift;
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u8 flags;
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u8 pad[2];
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} __attribute__((__packed__)); /* 32 bytes */
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whose data will be filled in by the hypervisor periodically. Only one
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write, or registration, is needed for each VCPU. The interval between
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updates of this structure is arbitrary and implementation-dependent.
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The hypervisor may update this structure at any time it sees fit until
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anything with bit0 == 0 is written to it.
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Fields have the following meanings:
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version: guest has to check version before and after grabbing
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time information and check that they are both equal and even.
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An odd version indicates an in-progress update.
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tsc_timestamp: the tsc value at the current VCPU at the time
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of the update of this structure. Guests can subtract this value
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from current tsc to derive a notion of elapsed time since the
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structure update.
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system_time: a host notion of monotonic time, including sleep
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time at the time this structure was last updated. Unit is
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nanoseconds.
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tsc_to_system_mul: multiplier to be used when converting
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tsc-related quantity to nanoseconds
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tsc_shift: shift to be used when converting tsc-related
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quantity to nanoseconds. This shift will ensure that
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multiplication with tsc_to_system_mul does not overflow.
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A positive value denotes a left shift, a negative value
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a right shift.
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The conversion from tsc to nanoseconds involves an additional
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right shift by 32 bits. With this information, guests can
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derive per-CPU time by doing:
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time = (current_tsc - tsc_timestamp)
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if (tsc_shift >= 0)
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time <<= tsc_shift;
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else
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time >>= -tsc_shift;
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time = (time * tsc_to_system_mul) >> 32
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time = time + system_time
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flags: bits in this field indicate extended capabilities
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coordinated between the guest and the hypervisor. Availability
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of specific flags has to be checked in 0x40000001 cpuid leaf.
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Current flags are:
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flag bit | cpuid bit | meaning
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-------------------------------------------------------------
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| | time measures taken across
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0 | 24 | multiple cpus are guaranteed to
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| | be monotonic
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-------------------------------------------------------------
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| | guest vcpu has been paused by
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1 | N/A | the host
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| | See 4.70 in api.txt
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-------------------------------------------------------------
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Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
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leaf prior to usage.
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MSR_KVM_WALL_CLOCK: 0x11
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data and functioning: same as MSR_KVM_WALL_CLOCK_NEW. Use that instead.
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This MSR falls outside the reserved KVM range and may be removed in the
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future. Its usage is deprecated.
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Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
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leaf prior to usage.
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MSR_KVM_SYSTEM_TIME: 0x12
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data and functioning: same as MSR_KVM_SYSTEM_TIME_NEW. Use that instead.
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This MSR falls outside the reserved KVM range and may be removed in the
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future. Its usage is deprecated.
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Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
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leaf prior to usage.
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The suggested algorithm for detecting kvmclock presence is then:
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if (!kvm_para_available()) /* refer to cpuid.txt */
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return NON_PRESENT;
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flags = cpuid_eax(0x40000001);
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if (flags & 3) {
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msr_kvm_system_time = MSR_KVM_SYSTEM_TIME_NEW;
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msr_kvm_wall_clock = MSR_KVM_WALL_CLOCK_NEW;
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return PRESENT;
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} else if (flags & 0) {
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msr_kvm_system_time = MSR_KVM_SYSTEM_TIME;
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msr_kvm_wall_clock = MSR_KVM_WALL_CLOCK;
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return PRESENT;
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} else
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return NON_PRESENT;
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MSR_KVM_ASYNC_PF_EN: 0x4b564d02
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data: Bits 63-6 hold 64-byte aligned physical address of a
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64 byte memory area which must be in guest RAM and must be
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zeroed. Bits 5-2 are reserved and should be zero. Bit 0 is 1
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when asynchronous page faults are enabled on the vcpu 0 when
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disabled. Bit 2 is 1 if asynchronous page faults can be injected
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when vcpu is in cpl == 0.
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First 4 byte of 64 byte memory location will be written to by
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the hypervisor at the time of asynchronous page fault (APF)
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injection to indicate type of asynchronous page fault. Value
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of 1 means that the page referred to by the page fault is not
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present. Value 2 means that the page is now available. Disabling
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interrupt inhibits APFs. Guest must not enable interrupt
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before the reason is read, or it may be overwritten by another
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APF. Since APF uses the same exception vector as regular page
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fault guest must reset the reason to 0 before it does
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something that can generate normal page fault. If during page
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fault APF reason is 0 it means that this is regular page
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fault.
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During delivery of type 1 APF cr2 contains a token that will
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be used to notify a guest when missing page becomes
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available. When page becomes available type 2 APF is sent with
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cr2 set to the token associated with the page. There is special
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kind of token 0xffffffff which tells vcpu that it should wake
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up all processes waiting for APFs and no individual type 2 APFs
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will be sent.
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If APF is disabled while there are outstanding APFs, they will
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not be delivered.
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Currently type 2 APF will be always delivered on the same vcpu as
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type 1 was, but guest should not rely on that.
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MSR_KVM_STEAL_TIME: 0x4b564d03
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data: 64-byte alignment physical address of a memory area which must be
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in guest RAM, plus an enable bit in bit 0. This memory is expected to
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hold a copy of the following structure:
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struct kvm_steal_time {
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__u64 steal;
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__u32 version;
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__u32 flags;
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__u32 pad[12];
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}
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whose data will be filled in by the hypervisor periodically. Only one
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write, or registration, is needed for each VCPU. The interval between
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updates of this structure is arbitrary and implementation-dependent.
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The hypervisor may update this structure at any time it sees fit until
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anything with bit0 == 0 is written to it. Guest is required to make sure
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this structure is initialized to zero.
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Fields have the following meanings:
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version: a sequence counter. In other words, guest has to check
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this field before and after grabbing time information and make
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sure they are both equal and even. An odd version indicates an
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in-progress update.
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flags: At this point, always zero. May be used to indicate
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changes in this structure in the future.
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steal: the amount of time in which this vCPU did not run, in
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nanoseconds. Time during which the vcpu is idle, will not be
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reported as steal time.
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MSR_KVM_EOI_EN: 0x4b564d04
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data: Bit 0 is 1 when PV end of interrupt is enabled on the vcpu; 0
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when disabled. Bit 1 is reserved and must be zero. When PV end of
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interrupt is enabled (bit 0 set), bits 63-2 hold a 4-byte aligned
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physical address of a 4 byte memory area which must be in guest RAM and
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must be zeroed.
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The first, least significant bit of 4 byte memory location will be
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written to by the hypervisor, typically at the time of interrupt
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injection. Value of 1 means that guest can skip writing EOI to the apic
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(using MSR or MMIO write); instead, it is sufficient to signal
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EOI by clearing the bit in guest memory - this location will
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later be polled by the hypervisor.
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Value of 0 means that the EOI write is required.
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It is always safe for the guest to ignore the optimization and perform
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the APIC EOI write anyway.
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Hypervisor is guaranteed to only modify this least
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significant bit while in the current VCPU context, this means that
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guest does not need to use either lock prefix or memory ordering
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primitives to synchronise with the hypervisor.
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However, hypervisor can set and clear this memory bit at any time:
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therefore to make sure hypervisor does not interrupt the
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guest and clear the least significant bit in the memory area
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in the window between guest testing it to detect
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whether it can skip EOI apic write and between guest
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clearing it to signal EOI to the hypervisor,
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guest must both read the least significant bit in the memory area and
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clear it using a single CPU instruction, such as test and clear, or
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compare and exchange.
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