118 lines
3.9 KiB
Plaintext
118 lines
3.9 KiB
Plaintext
SAMSUNG USB-PHY controllers
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** Samsung's usb 2.0 phy transceiver
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The Samsung's usb 2.0 phy transceiver is used for controlling
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usb 2.0 phy for s3c-hsotg as well as ehci-s5p and ohci-exynos
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usb controllers across Samsung SOCs.
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TODO: Adding the PHY binding with controller(s) according to the under
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development generic PHY driver.
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Required properties:
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Exynos4210:
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- compatible : should be "samsung,exynos4210-usb2phy"
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- reg : base physical address of the phy registers and length of memory mapped
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region.
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- clocks: Clock IDs array as required by the controller.
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- clock-names: names of clock correseponding IDs clock property as requested
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by the controller driver.
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Exynos5250:
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- compatible : should be "samsung,exynos5250-usb2phy"
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- reg : base physical address of the phy registers and length of memory mapped
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region.
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Optional properties:
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- #address-cells: should be '1' when usbphy node has a child node with 'reg'
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property.
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- #size-cells: should be '1' when usbphy node has a child node with 'reg'
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property.
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- ranges: allows valid translation between child's address space and parent's
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address space.
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- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
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interface for usb-phy. It should provide the following information required by
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usb-phy controller to control phy.
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- reg : base physical address of PHY_CONTROL registers.
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The size of this register is the total sum of size of all PHY_CONTROL
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registers that the SoC has. For example, the size will be
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'0x4' in case we have only one PHY_CONTROL register (e.g.
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OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
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and, '0x8' in case we have two PHY_CONTROL registers (e.g.
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USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
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and so on.
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Example:
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- Exynos4210
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usbphy@125B0000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "samsung,exynos4210-usb2phy";
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reg = <0x125B0000 0x100>;
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ranges;
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clocks = <&clock 2>, <&clock 305>;
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clock-names = "xusbxti", "otg";
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usbphy-sys {
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/* USB device and host PHY_CONTROL registers */
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reg = <0x10020704 0x8>;
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};
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};
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** Samsung's usb 3.0 phy transceiver
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Starting exynso5250, Samsung's SoC have usb 3.0 phy transceiver
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which is used for controlling usb 3.0 phy for dwc3-exynos usb 3.0
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controllers across Samsung SOCs.
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Required properties:
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Exynos5250:
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- compatible : should be "samsung,exynos5250-usb3phy"
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- reg : base physical address of the phy registers and length of memory mapped
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region.
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- clocks: Clock IDs array as required by the controller.
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- clock-names: names of clocks correseponding to IDs in the clock property
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as requested by the controller driver.
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Optional properties:
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- #address-cells: should be '1' when usbphy node has a child node with 'reg'
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property.
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- #size-cells: should be '1' when usbphy node has a child node with 'reg'
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property.
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- ranges: allows valid translation between child's address space and parent's
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address space.
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- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
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interface for usb-phy. It should provide the following information required by
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usb-phy controller to control phy.
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- reg : base physical address of PHY_CONTROL registers.
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The size of this register is the total sum of size of all PHY_CONTROL
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registers that the SoC has. For example, the size will be
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'0x4' in case we have only one PHY_CONTROL register (e.g.
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OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
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and, '0x8' in case we have two PHY_CONTROL registers (e.g.
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USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
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and so on.
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Example:
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usbphy@12100000 {
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compatible = "samsung,exynos5250-usb3phy";
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reg = <0x12100000 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&clock 1>, <&clock 286>;
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clock-names = "ext_xtal", "usbdrd30";
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usbphy-sys {
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/* USB device and host PHY_CONTROL registers */
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reg = <0x10040704 0x8>;
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};
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};
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