188 lines
8.4 KiB
Plaintext
188 lines
8.4 KiB
Plaintext
* Universal Flash Storage (UFS) Host Controller
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UFSHC nodes are defined to describe on-chip UFS host controllers.
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Each UFS controller instance should have its own node.
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Required properties:
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- compatible : compatible list, contains "jedec,ufs-1.1"
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- interrupts : <interrupt mapping for UFS host controller IRQ>
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- reg : <registers mapping>
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first entry should contain UFS host controller register address space (mandatory),
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second entry is the device ref. clock control register map (optional).
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Optional properties:
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- phys : phandle to UFS PHY node
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- phy-names : the string "ufsphy" when is found in a node, along
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with "phys" attribute, provides phandle to UFS PHY node
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- vdd-hba-supply : phandle to UFS host controller supply regulator node
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- vcc-supply : phandle to VCC supply regulator node
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- vccq-supply : phandle to VCCQ supply regulator node
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- vccq2-supply : phandle to VCCQ2 supply regulator node
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- vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
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or 2.7-3.6V. This boolean property when set, specifies
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to use low voltage range of 1.7-1.95V. Note for external
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UFS cards this property is invalid and valid VCC range is
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always 2.7-3.6V.
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- vcc-max-microamp : specifies max. load that can be drawn from vcc supply
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- vccq-max-microamp : specifies max. load that can be drawn from vccq supply
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- vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
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- <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
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- clocks : List of phandle and clock specifier pairs
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- clock-names : List of clock input name strings sorted in the same
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order as the clocks property.
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- freq-table-hz : Array of <min max> operating frequencies stored in the same
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order as the clocks property. If this property is not
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defined or a value in the array is "0" then it is assumed
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that the frequency is set by the parent clock or a
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fixed rate clock source.
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- rpm-level : UFS Runtime power management level. Following PM levels are suppported:
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0 - Both UFS device and Link in active state (Highest power consumption)
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1 - UFS device in active state but Link in Hibern8 state
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2 - UFS device in Sleep state but Link in active state
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3 - UFS device in Sleep state and Link in hibern8 state (default PM level)
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4 - UFS device in Power-down state and Link in Hibern8 state
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5 - UFS device in Power-down state and Link in OFF state (Lowest power consumption)
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- spm-level : UFS System power management level. Allowed PM levels are same as rpm-level.
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- ufs-qcom-crypto : phandle to UFS-QCOM ICE (Inline Cryptographic Engine) node
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- lanes-per-direction: number of lanes available per direction - either 1 or 2.
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Note that it is assume same number of lanes is used both directions at once.
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If not specified, default is 2 lanes per direction.
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Note: If above properties are not defined it can be assumed that the supply
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regulators or clocks are always on.
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Example:
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ufshc@0xfc598000 {
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compatible = "jedec,ufs-1.1";
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reg = <0xfc598000 0x800>, <0xfd512074 0x4>;
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interrupts = <0 28 0>;
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ufs-qcom-crypto = <&ufs_ice>;
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vdd-hba-supply = <&xxx_reg0>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&xxx_reg1>;
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vcc-supply-1p8;
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vccq-supply = <&xxx_reg2>;
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vccq2-supply = <&xxx_reg3>;
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vcc-max-microamp = 500000;
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vccq-max-microamp = 200000;
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vccq2-max-microamp = 200000;
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clocks = <&core 0>, <&ref 0>, <&iface 0>;
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clock-names = "core_clk", "ref_clk", "iface_clk";
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freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;
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rpm-level = <3>;
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spm-level = <5>;
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};
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==== UFS QCOM platform driver properties =====
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* For UFS host controller in QCOM platform following clocks are required -
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Controller clock source -
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"core_clk_src", max-clock-frequency-hz = 200MHz
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"core_clk_unipro_src" - Some controller versions require separate core clock for UniPro.
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This clock represents the source clock for the core clock of UniPro.
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Controller System clock branch:
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"core_clk" - Controller core clock
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"core_clk_unipro" - Core clock for UniPro
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AHB/AXI interface clocks:
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"iface_clk" - AHB interface clock
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"bus_clk" - AXI bus master clock
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PHY to controller symbol synchronization clocks:
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"rx_lane0_sync_clk" - RX Lane 0
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"rx_lane1_sync_clk" - RX Lane 1
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"tx_lane0_sync_clk" - TX Lane 0
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"tx_lane1_sync_clk" - TX Lane 1
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Optional reference clock input to UFS device
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"ref_clk", max-clock-frequency-hz = 19.2MHz
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* Following bus parameters are required -
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- qcom,msm-bus,name
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- qcom,msm-bus,num-cases
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- qcom,msm-bus,num-paths
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- qcom,msm-bus,vectors-KBps
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For the above four properties please refer to
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Documentation/devicetree/bindings/arm/msm/msm_bus.txt
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Note: The instantaneous bandwidth (IB) value in the vectors-KBps field should
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be zero as UFS data transfer path doesn't have latency requirements and
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voting for aggregated bandwidth (AB) should take care of providing
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optimum throughput requested.
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- qcom,bus-vector-names: specifies string IDs for the corresponding
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bus vectors in the same order as qcom,msm-bus,vectors-KBps property.
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* The following parameters are optional, but required in order for PM QoS to be
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enabled and functional in the driver:
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- qcom,pm-qos-cpu-groups: arrays of unsigned integers representing the cpu groups.
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The number of values in the array defines the number of cpu-groups.
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Each value is a bit-mask defining the cpus that take part in that cpu group.
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i.e. if bit N is set, then cpuN is a part of the cpu group. So basically,
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a cpu group corelated to a cpu cluster.
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A PM QoS request object is maintained for each cpu-group.
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- qcom,pm-qos-cpu-group-latency-us: array of values used for PM QoS voting, one for each cpu-group defined.
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the number of values must match the number of values defined in
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qcom,pm-qos-cpu-mask property.
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- qcom,pm-qos-default-cpu: PM QoS voting is based on the cpu associated with each IO request by the block layer.
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This defined the default cpu used for PM QoS voting in case a specific cpu value is not available.
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Example:
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ufshc@0xfc598000 {
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...
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qcom,msm-bus,name = "ufs1";
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qcom,msm-bus,num-cases = <22>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<95 512 0 0>, <1 650 0 0>, /* No vote */
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<95 512 922 0>, <1 650 1000 0>, /* PWM G1 */
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<95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */
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<95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */
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<95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */
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<95 512 1844 0>, <1 650 1000 0>, /* PWM G1 L2 */
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<95 512 3688 0>, <1 650 1000 0>, /* PWM G2 L2 */
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<95 512 7376 0>, <1 650 1000 0>, /* PWM G3 L2 */
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<95 512 14752 0>, <1 650 1000 0>, /* PWM G4 L2 */
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<95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */
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<95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */
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<95 512 511181 0>, <1 650 1000 0>, /* HS G3 RA */
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<95 512 255591 0>, <1 650 1000 0>, /* HS G1 RA L2 */
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<95 512 511181 0>, <1 650 1000 0>, /* HS G2 RA L2 */
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<95 512 1022362 0>, <1 650 1000 0>, /* HS G3 RA L2 */
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<95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */
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<95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */
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<95 512 596378 0>, <1 650 1000 0>, /* HS G3 RB */
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<95 512 298189 0>, <1 650 1000 0>, /* HS G1 RB L2 */
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<95 512 596378 0>, <1 650 1000 0>, /* HS G2 RB L2 */
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<95 512 1192756 0>, <1 650 1000 0>, /* HS G3 RB L2 */
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<95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */
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qcom,bus-vector-names = "MIN",
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"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
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"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
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"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
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"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
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"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
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"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
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"MAX";
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qcom,pm-qos-cpu-groups = <0x03 0x0C>; /* group0: cpu0, cpu1, group1: cpu2, cpu3 */
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qcom,pm-qos-cpu-group-latency-us = <200 300>; /* group0: 200us, group1: 300us */
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qcom,pm-qos-default-cpu = <0>;
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};
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This is an example to a variant sub-node of ufshc:
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ufs_variant {
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compatible = "qcom,ufs_variant";
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};
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This sub-node holds various specific information that is not defined in the
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standard and that may differ between platforms.
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