74 lines
2.6 KiB
Plaintext
74 lines
2.6 KiB
Plaintext
MSM Array Power Mux (msm-apm)
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In some MSM designs, the CPU and caches contain logic which can be powered by
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multiple rails. The APM controller exists to enable the selection of the power
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rail supplying these arrays. Since a given supply may drop below the array
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SRAM minimum operating voltage, the APM controller can be used to request a
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switch to a power supply that will guarantee logic state retention.
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Required properties
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- compatible: "qcom,msm-apm", "qcom,msmtitanium-apm"
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- reg: Specifies physical base address and size of memory mapped regions
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containing the APM controller, APCS CSR, APC PLL controller, and
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SPM event registers.
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- reg-names: List of strings identifying the reg property entries. This list must
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contain: "pm-apcc-glb", "apcs-csr", "apc0-pll-ctl", "apc1-pll-ctl",
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"apc0-cpu0-spm", "apc0-cpu1-spm", "apc1-cpu0-spm", "apc1-cpu1-spm",
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"apc0-l2-spm", and "apc1-l2-spm".
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Optional properties
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- qcom,clock-source-override: Specify this property to request a switch of the APC0 and APC1
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clock sources to GPLL0 before the APM switch begins and to
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switch back to the original clock source after the APM switch
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completes.
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- qcom,apm-post-halt-delay: The APM controller post halt delay counter value that SW needs
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to program one time before starting the APM HW controller for
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msmtitanium target.
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- qcom,apm-halt-clk-delay: The APM controller halt clock delay counter value that SW
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needs to program one time before starting the APM HW controller
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for msmtitanium target.
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- qcom,apm-resume-clk-delay: The APM controller resume clock delay counter value that SW
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needs to program one time before starting the APM HW controller
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for msmtitanium target.
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- qcom,apm-sel-switch-delay: The APM controller switch selection delay counter value that SW
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needs to program one time before starting the APM HW controller
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for msmtitanium target.
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MSM APM Users
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Required properties:
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- qcom,apm-ctrl: phandle of APM controller device node
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Example:
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apc_apm: apm@099e0000 {
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compatible = "qcom,msm-apm";
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reg = <0x099e0000 0x1000>,
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<0x09820000 0x10000>,
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<0x06400050 0x8>,
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<0x06480050 0x8>,
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<0x09981068 0x8>,
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<0x09991068 0x8>,
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<0x099b1068 0x8>,
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<0x099c1068 0x8>,
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<0x099a1068 0x8>,
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<0x099d1068 0x8>;
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reg-names = "pm-apcc-glb",
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"apcs-csr",
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"apc0-pll-ctl",
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"apc1-pll-ctl",
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"apc0-cpu0-spm",
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"apc0-cpu1-spm",
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"apc1-cpu0-spm",
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"apc1-cpu1-spm",
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"apc0-l2-spm",
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"apc1-l2-spm";
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qcom,apm-post-halt-delay = <0x2>;
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qcom,apm-halt-clk-delay = <0x11>;
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qcom,apm-resume-clk-delay = <0x10>;
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qcom,apm-sel-switch-delay = <0x01>;
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foo_user {
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...
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qcom,apm-ctrl = <&apc_apm>;
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};
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