192 lines
6.0 KiB
Plaintext
192 lines
6.0 KiB
Plaintext
Qualcomm Technologies, Inc. MDM9607 TLMM block
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This binding describes the Top Level Mode Multiplexer block found in the
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MDM9607 platform.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be "qcom,mdm9607-pinctrl"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: the base address and size of the TLMM register space.
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: should specify the TLMM summary IRQ.
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- interrupt-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as an interrupt controller
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- #interrupt-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/interrupt-controller/irq.h>
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- gpio-controller:
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Usage: required
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Value type: <none>
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Definition: identifies this node as a gpio controller
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- #gpio-cells:
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Usage: required
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Value type: <u32>
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Definition: must be 2. Specifying the pin number and flags, as defined
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in <dt-bindings/gpio/gpio.h>
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- qcom,tlmm-emmc-boot-select:
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Usage: optional
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Value type: <u32>
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Definition: selects the bit-field position to set.
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
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a general description of GPIO and interrupt bindings.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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The pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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PIN CONFIGURATION NODES:
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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- pins:
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Usage: required
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Value type: <string-array>
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Definition: List of gpio pins affected by the properties specified in
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this subnode. Valid pins are:
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gpio0-gpio79,
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sdc1_clk,
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sdc1_cmd,
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sdc1_data,
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sdc2_clk,
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sdc2_cmd,
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sdc2_data,
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qdsd_clk,
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qdsd_cmd,
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qdsd_data0,
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qdsd_data1,
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qdsd_data2,
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qdsd_data3
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- function:
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Usage: required
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Value type: <string>
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Definition: Specify the alternative function to be configured for the
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specified pins. Functions are only valid for gpio pins.
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Valid values are:
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blsp_spi3, blsp_uart3, qdss_tracedata_a, bimc_dte1, blsp_i2c3,
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qdss_traceclk_a, bimc_dte0, qdss_cti_trig_in_a1, blsp_spi2,
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blsp_uart2, blsp_uim2, blsp_i2c2, qdss_tracectl_a, sensor_int2,
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blsp_spi5, blsp_uart5, ebi2_lcd, m_voc, sensor_int3, sensor_en,
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blsp_i2c5, ebi2_a, qdss_tracedata_b, sensor_rst, blsp2_spi,
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blsp_spi1, blsp_uart1, blsp_uim1, blsp3_spi, gcc_gp2_clk_b,
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gcc_gp3_clk_b, blsp_i2c1, gcc_gp1_clk_b, blsp_spi4, blsp_uart4,
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rcm_marker1, blsp_i2c4, qdss_cti_trig_out_a1, rcm_marker2,
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qdss_cti_trig_out_a0, blsp_spi6, blsp_uart6, pri_mi2s_ws_a,
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ebi2_lcd_te_b, blsp1_spi, backlight_en_b, pri_mi2s_data0_a,
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pri_mi2s_data1_a, blsp_i2c6, ebi2_a_d_8_b, pri_mi2s_sck_a,
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ebi2_lcd_cs_n_b, touch_rst, pri_mi2s_mclk_a, pwr_nav_enabled_a,
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ts_int, sd_write, pwr_crypto_enabled_a, codec_rst, adsp_ext,
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atest_combodac_to_gpio_native, uim2_data, gmac_mdio, gcc_gp1_clk_a,
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uim2_clk, gcc_gp2_clk_a, eth_irq, uim2_reset, gcc_gp3_clk_a,
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eth_rst, uim2_present, prng_rosc, uim1_data, uim1_clk,
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uim1_reset, uim1_present, gcc_plltest, uim_batt, coex_uart,
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codec_int, qdss_cti_trig_in_a0, atest_bbrx1, cri_trng0, atest_bbrx0,
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cri_trng, qdss_cti_trig_in_b0, atest_gpsadc_dtest0_native,
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qdss_cti_trig_out_b0, qdss_tracectl_b, qdss_traceclk_b, pa_indicator,
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modem_tsync, nav_tsync_out_a, nav_ptp_pps_in_a, ptp_pps_out_a,
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gsm0_tx, qdss_cti_trig_in_b1, cri_trng1, qdss_cti_trig_out_b1,
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ssbi1, atest_gpsadc_dtest1_native, ssbi2, atest_char3, atest_char2,
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atest_char1, atest_char0, atest_char, ebi0_wrcdc, ldo_update,
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gcc_tlmm, ldo_en, dbg_out, atest_tsens, lcd_rst, wlan_en1,
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nav_tsync_out_b, nav_ptp_pps_in_b, ptp_pps_out_b, pbs0, sec_mi2s,
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pwr_modem_enabled_a, pbs1, pwr_modem_enabled_b, pbs2, pwr_nav_enabled_b,
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pwr_crypto_enabled_b, gpio
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- bias-disable:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configued as no pull.
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- bias-pull-down:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configued as pull down.
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- bias-pull-up:
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Usage: optional
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Value type: <none>
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Definition: The specified pins should be configued as pull up.
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- output-high:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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high.
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Not valid for sdc pins.
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- output-low:
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Usage: optional
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Value type: <none>
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Definition: The specified pins are configured in output mode, driven
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low.
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Not valid for sdc pins.
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- drive-strength:
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Usage: optional
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Value type: <u32>
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Definition: Selects the drive strength for the specified pins, in mA.
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Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
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Example:
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tlmm: pinctrl@01010000 {
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compatible = "qcom,mdm9607-pinctrl";
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reg = <0x01010000 0x300000>;
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interrupts = <0 208 0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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qcom,tlmm-emmc-boot-select = <0x1>;
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uart_console_active: uart_console_active {
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mux {
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pins = "gpio8", "gpio9";
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function = "blsp_uart5";
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};
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config {
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pins = "gpio8", "gpio9";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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