48 lines
1.8 KiB
Plaintext
48 lines
1.8 KiB
Plaintext
* Renesas RCar PCIe interface
|
|
|
|
Required properties:
|
|
- compatible: should contain one of the following
|
|
"renesas,pcie-r8a7779", "renesas,pcie-r8a7790", "renesas,pcie-r8a7791"
|
|
- reg: base address and length of the pcie controller registers.
|
|
- #address-cells: set to <3>
|
|
- #size-cells: set to <2>
|
|
- bus-range: PCI bus numbers covered
|
|
- device_type: set to "pci"
|
|
- ranges: ranges for the PCI memory and I/O regions.
|
|
- dma-ranges: ranges for the inbound memory regions.
|
|
- interrupts: two interrupt sources for MSI interrupts, followed by interrupt
|
|
source for hardware related interrupts (e.g. link speed change).
|
|
- #interrupt-cells: set to <1>
|
|
- interrupt-map-mask and interrupt-map: standard PCI properties
|
|
to define the mapping of the PCIe interface to interrupt
|
|
numbers.
|
|
- clocks: from common clock binding: clock specifiers for the PCIe controller
|
|
and PCIe bus clocks.
|
|
- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
|
|
|
|
Example:
|
|
|
|
SoC specific DT Entry:
|
|
|
|
pcie: pcie@fe000000 {
|
|
compatible = "renesas,pcie-r8a7791";
|
|
reg = <0 0xfe000000 0 0x80000>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0x00 0xff>;
|
|
device_type = "pci";
|
|
ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
|
|
0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
|
|
0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
|
|
0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
|
|
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
|
|
0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
|
|
interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic 0 116 4>;
|
|
clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>;
|
|
clock-names = "pcie", "pcie_bus";
|
|
status = "disabled";
|
|
};
|