247 lines
9.9 KiB
Plaintext
247 lines
9.9 KiB
Plaintext
MSM PCIe
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MSM PCI express root complex
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Required properties:
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- compatible: should be "qcom,pci-msm"
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- cell-index: defines root complex ID.
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- #address-cells: Should provide a value of 0.
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- reg: should contain PCIe register maps.
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- reg-names: indicates various resources passed to driver by name.
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Should be "parf", "phy", "dm_core", "elbi", "conf", "io", "bars".
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These correspond to different modules within the PCIe core.
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- ranges: For details of ranges properties, please refer to:
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"Documentation\devicetree\bindings\pci\pci.txt"
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- interrupts: Should be in the format <0 1 2> and it is an index to the
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interrupt-map that contains PCIe related interrupts.
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- #interrupt-cells: Should provide a value of 1.
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- #interrupt-map-mask: should provide a value of 0xffffffff.
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- interrupt-map: Must create mapping for the number of interrupts
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that are defined in above interrupts property.
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For PCIe device node, it should define 12 mappings for
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the corresponding PCIe interrupts supporting the specification.
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- interrupt-names: indicates interrupts passed to driver by name.
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Should be "int_msi", "int_a", "int_b", "int_c", "int_d",
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"int_pls_pme", "int_pme_legacy", "int_pls_err",
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"int_aer_legacy", "int_pls_link_up",
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"int_pls_link_down", "int_bridge_flush_n",
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"msi_0", "msi_1", "msi_2", "msi_3",
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"msi_4", "msi_5", "msi_6", "msi_7",
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"msi_8", "msi_9", "msi_10", "msi_11",
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"msi_12", "msi_13", "msi_14", "msi_15",
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"msi_16", "msi_17", "msi_18", "msi_19",
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"msi_20", "msi_21", "msi_22", "msi_23",
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"msi_24", "msi_25", "msi_26", "msi_27",
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"msi_28", "msi_29", "msi_30", "msi_31"
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These correspond to the standard PCIe specification to support
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MSIs, virtual IRQ's (INT#), link state notifications.
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- perst-gpio: PERST GPIO specified by PCIe spec.
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- wake-gpio: WAKE GPIO specified by PCIe spec.
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- <supply-name>-supply: phandle to the regulator device tree node.
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Refer to the schematics for the corresponding voltage regulators.
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vreg-1.8-supply: phandle to the analog supply for the PCIe controller.
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vreg-3.3-supply: phandle to the analog supply for the PCIe controller.
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vreg-0.9-supply: phandle to the analog supply for the PCIe controller.
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Optional Properties:
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- qcom,<supply-name>-voltage-level: specifies voltage levels for supply.
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Should be specified in pairs (max, min, optimal), units uV.
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- clkreq-gpio: CLKREQ GPIO specified by PCIe spec.
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- qcom,ep-gpio: GPIO which enables a certain type of endpoint for link training.
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- pinctrl-names: The state name of the pin configuration.
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supports: "default", "sleep"
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- pinctrl-0: For details of pinctrl properties, please refer to:
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"Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt"
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- pinctrl-1: For details of pinctrl properties, please refer to:
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"Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt"
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- clocks: list of clock phandles
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- clock-names: list of names of clock inputs.
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Should be "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo";
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- max-clock-frequency-hz: list of the maximum operating frequencies stored
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in the same order of clock names;
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- qcom,l0s-supported: L0s is supported.
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- qcom,l1-supported: L1 is supported.
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- qcom,l1ss-supported: L1 sub-states (L1ss) is supported.
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- qcom,aux-clk-sync: The AUX clock is synchronous to the Core clock to
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support L1ss.
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- qcom,common-clk-en: Enables the common clock configuration for the endpoint.
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- qcom,clk-power-manage-en: Enables the clock power management for the
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endpoint.
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- qcom,n-fts: The number of fast training sequences sent when the link state
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is changed from L0s to L0.
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- qcom,pcie-phy-ver: version of PCIe PHY.
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- qcom,use-19p2mhz-aux-clk: The frequency of PCIe AUX clock is 19.2MHz.
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- qcom,ep-wakeirq: The endpoint will issue wake signal when it is up, and the
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root complex has the capability to enumerate the endpoint for this case.
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- qcom,msi-gicm-addr: MSI address for GICv2m.
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- qcom,msi-gicm-base: MSI IRQ base for GICv2m.
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- qcom,ext-ref-clk: The reference clock is external.
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- iommus: the phandle and stream IDs for the SMMU used by this root
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complex. This should be used in separate nodes from the main root
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complex nodes, and is the only property needed in that case.
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- qcom,common-phy: There is a common phy for all the Root Complexes.
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- qcom,smmu-exist: PCIe uses a SMMU.
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- qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become
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stable after power on, before de-assert the PERST to the endpoint.
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- qcom,cpl-timeout: Completion timeout value. This value specifies the time range
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which the root complex will send out a completion packet if there is no response
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from the endpoint.
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- linux,pci-domain: For details of pci-domains properties, please refer to:
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"Documentation/devicetree/bindings/pci/pci.txt"
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- qcom,tlp-rd-size: The max TLP read size (Calculation: 128 times 2 to the
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tlp-rd-size power).
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- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
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below optional properties:
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- qcom,msm-bus,name
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- qcom,msm-bus,num-cases
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- qcom,msm-bus,num-paths
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- qcom,msm-bus,vectors-KBps
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- qcom,scm-dev-id: If present then device id value is passed to secure channel
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manager(scm) driver. scm driver uses this device id to restore PCIe
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controller related security configuration after coming out of the controller
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power collapse.
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Example:
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pcie0: qcom,pcie@fc520000 {
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compatible = "qcom,msm_pcie";
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cell-index = <0>;
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#address-cells = <0>;
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reg = <0xfc520000 0x2000>,
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<0xfc526000 0x1000>,
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<0xff000000 0x1000>,
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<0xff001000 0x1000>,
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<0xff100000 0x1000>,
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<0xff200000 0x100000>,
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<0xff300000 0xd00000>;
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reg-names = "parf", "dm_core", "elbi",
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"conf", "io", "bars";
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ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
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<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4 5 6 7 8 9 10 11
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12 13 14 15 16 17 18 19 20
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21 22 23 24 25 26 27 28 29
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30 31 32 33 34 35 36 37 38
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39 40 41 42 43>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0x0 0x0 0x0 0 &intc 0 405 0
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0x0 0x0 0x0 1 &intc 0 244 0
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0x0 0x0 0x0 2 &intc 0 245 0
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0x0 0x0 0x0 3 &intc 0 247 0
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0x0 0x0 0x0 4 &intc 0 248 0
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0x0 0x0 0x0 5 &intc 0 249 0
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0x0 0x0 0x0 6 &intc 0 250 0
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0x0 0x0 0x0 7 &intc 0 251 0
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0x0 0x0 0x0 8 &intc 0 252 0
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0x0 0x0 0x0 9 &intc 0 253 0
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0x0 0x0 0x0 10 &intc 0 254 0
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0x0 0x0 0x0 11 &intc 0 255 0
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0x0 0x0 0x0 12 &intc 0 448 0
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0x0 0x0 0x0 13 &intc 0 449 0
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0x0 0x0 0x0 14 &intc 0 450 0
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0x0 0x0 0x0 15 &intc 0 451 0
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0x0 0x0 0x0 16 &intc 0 452 0
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0x0 0x0 0x0 17 &intc 0 453 0
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0x0 0x0 0x0 18 &intc 0 454 0
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0x0 0x0 0x0 19 &intc 0 455 0
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0x0 0x0 0x0 20 &intc 0 456 0
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0x0 0x0 0x0 21 &intc 0 457 0
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0x0 0x0 0x0 22 &intc 0 458 0
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0x0 0x0 0x0 23 &intc 0 459 0
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0x0 0x0 0x0 24 &intc 0 460 0
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0x0 0x0 0x0 25 &intc 0 461 0
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0x0 0x0 0x0 26 &intc 0 462 0
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0x0 0x0 0x0 27 &intc 0 463 0
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0x0 0x0 0x0 28 &intc 0 464 0
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0x0 0x0 0x0 29 &intc 0 465 0
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0x0 0x0 0x0 30 &intc 0 466 0
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0x0 0x0 0x0 31 &intc 0 467 0
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0x0 0x0 0x0 32 &intc 0 468 0
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0x0 0x0 0x0 33 &intc 0 469 0
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0x0 0x0 0x0 34 &intc 0 470 0
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0x0 0x0 0x0 35 &intc 0 471 0
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0x0 0x0 0x0 36 &intc 0 472 0
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0x0 0x0 0x0 37 &intc 0 473 0
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0x0 0x0 0x0 38 &intc 0 474 0
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0x0 0x0 0x0 39 &intc 0 475 0
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0x0 0x0 0x0 40 &intc 0 476 0
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0x0 0x0 0x0 41 &intc 0 477 0
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0x0 0x0 0x0 42 &intc 0 478 0
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0x0 0x0 0x0 43 &intc 0 479 0>;
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interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
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"int_pls_pme", "int_pme_legacy", "int_pls_err",
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"int_aer_legacy", "int_pls_link_up",
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"int_pls_link_down", "int_bridge_flush_n",
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"msi_0", "msi_1", "msi_2", "msi_3",
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"msi_4", "msi_5", "msi_6", "msi_7",
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"msi_8", "msi_9", "msi_10", "msi_11",
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"msi_12", "msi_13", "msi_14", "msi_15",
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"msi_16", "msi_17", "msi_18", "msi_19",
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"msi_20", "msi_21", "msi_22", "msi_23",
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"msi_24", "msi_25", "msi_26", "msi_27",
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"msi_28", "msi_29", "msi_30", "msi_31";
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perst-gpio = <&msmgpio 70 0>;
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wake-gpio = <&msmgpio 69 0>;
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clkreq-gpio = <&msmgpio 68 0>;
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qcom,ep-gpio = <&tlmm 94 0>;
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gdsc-vdd-supply = <&gdsc_pcie_0>;
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vreg-1.8-supply = <&pma8084_l12>;
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vreg-0.9-supply = <&pma8084_l4>;
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vreg-3.3-supply = <&wlan_vreg>;
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qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;
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qcom,vreg-0.9-voltage-level = <950000 950000 24000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
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pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_sleep &pcie0_wake_sleep>;
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clocks = <&clock_gcc clk_gcc_pcie_0_pipe_clk>,
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<&clock_rpm clk_ln_bb_clk>,
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<&clock_gcc clk_gcc_pcie_0_aux_clk>,
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<&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>,
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<&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>,
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<&clock_gcc clk_gcc_pcie_0_slv_axi_clk>,
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<&clock_gcc clk_pcie_0_phy_ldo>,
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<&clock_gcc clk_gcc_pcie_phy_0_reset>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo";
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max-clock-frequency-hz = <125000000>, <0>, <1000000>,
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<0>, <0>, <0>, <0>;
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qcom,l0s-supported;
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qcom,l1-supported;
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qcom,l1ss-supported;
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qcom,aux-clk-sync;
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qcom,n-fts = <0x50>;
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qcom,pcie-phy-ver = <1>;
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qcom,ep-wakeirq;
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qcom,msi-gicm-addr = <0xf9040040>;
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qcom,msi-gicm-base = <0x160>;
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qcom,ext-ref-clk;
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qcom,tlp-rd-size = <0x5>;
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qcom,common-phy;
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qcom,smmu-exist;
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qcom,ep-latency = <100>;
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qcom,cpl-timeout = <0x2>;
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iommus = <&anoc0_smmu>;
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qcom,msm-bus,name = "pcie0";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<45 512 0 0>,
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<45 512 500 800>;
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qcom,scm-dev-id = <11>;
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};
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