160 lines
5.4 KiB
Plaintext
160 lines
5.4 KiB
Plaintext
* Qualcomm MSM ISPIF
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Required properties:
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- cell-index: ispif hardware core index
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- compatible :
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- "qcom,ispif"
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- "qcom,ispif-v3.0"
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- reg : offset and length of the register set for the device
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for the ispif operating in compatible mode.
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- reg-names : should specify relevant names to each reg property defined.
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- interrupts : should contain the ispif interrupt.
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- interrupt-names : should specify relevant names to each interrupts
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property defined.
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- camss-vdd-supply: phandle to GDSC regulator.
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- mmagic-vdd-supply: phandle to mmagic regulator.
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- vfe0-vdd-supply: phandle to vfe0 regulator.
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- vfe1-vdd-supply: phandle to vfe1 regulator.
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- clocks: list of phandles to the clock controller device and coresponding
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clock names.
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- clock-names: name of the clocks required for the device used by the consumer.
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- qcom,clock-rates: clock rate in Hz.
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- qcom,clock-control: The valid fields are "NO_SET_RATE", "INIT_RATE" and
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"SET_RATE". "NO_SET_RATE" the corresponding clock is enabled without setting
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the rate assuming some other driver has already set it to appropriate rate.
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"INIT_RATE" clock rate is not queried assuming some other driver has set
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the clock rate and ispif will set the the clock to this rate.
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"SET_RATE" clock is enabled and the rate is set to the value specified
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in the property qcom,clock-rates.
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Optional properties:
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- qcom,num-isps: The number of ISPs the ISPIF module is connected to. If not set
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the default value used is 1
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Example:
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qcom,ispif@fda0a000 {
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cell-index = <0>;
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compatible = "qcom,ispif";
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reg = <0xfda0a000 0x300>;
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reg-names = "ispif";
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interrupts = <0 55 0>;
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interrupt-names = "ispif";
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camss-vdd-supply = <&gdsc_camss_top>;
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mmagic-vdd-supply = <&gdsc_mmagic_camss>;
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vfe0-vdd-supply = <&gdsc_vfe0>;
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vfe1-vdd-supply = <&gdsc_vfe1>;
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clocks = <&clock_mmss clk_camss_ispif_ahb_clk>,
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<&clock_mmss clk_csi0_clk_src>,
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<&clock_mmss clk_camss_csi0_clk>,
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<&clock_mmss clk_camss_csi0rdi_clk>,
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<&clock_mmss clk_camss_csi0pix_clk>,
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<&clock_mmss clk_csi1_clk_src>,
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<&clock_mmss clk_camss_csi1_clk>,
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<&clock_mmss clk_camss_csi1rdi_clk>,
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<&clock_mmss clk_camss_csi1pix_clk>,
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<&clock_mmss clk_csi2_clk_src>,
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<&clock_mmss clk_camss_csi2_clk>,
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<&clock_mmss clk_camss_csi2rdi_clk>,
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<&clock_mmss clk_camss_csi2pix_clk>,
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<&clock_mmss clk_csi3_clk_src>,
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<&clock_mmss clk_camss_csi3_clk>,
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<&clock_mmss clk_camss_csi3rdi_clk>,
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<&clock_mmss clk_camss_csi3pix_clk>,
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<&clock_mmss clk_vfe0_clk_src>,
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<&clock_mmss clk_camss_vfe0_clk>,
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<&clock_mmss clk_camss_csi_vfe0_clk>,
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<&clock_mmss clk_vfe1_clk_src>,
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<&clock_mmss clk_camss_vfe1_clk>,
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<&clock_mmss clk_camss_csi_vfe1_clk>;
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clock-names = "ispif_ahb_clk",
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"csi0_src_clk", "csi0_clk",
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"csi0_pix_clk", "csi0_rdi_clk",
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"csi1_src_clk", "csi1_clk",
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"csi1_pix_clk", "csi1_rdi_clk",
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"csi2_src_clk", "csi2_clk",
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"csi2_pix_clk", "csi2_rdi_clk",
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"csi3_src_clk", "csi3_clk",
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"csi3_pix_clk", "csi3_rdi_clk",
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"vfe0_clk_src", "camss_vfe_vfe0_clk", "camss_csi_vfe0_clk",
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"vfe1_clk_src", "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";
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qcom,clock-rates = <0
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200000000 0 0 0
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200000000 0 0 0
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200000000 0 0 0
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200000000 0 0 0
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0 0 0
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0 0 0>;
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qcom,clock-control = "NO_SET_RATE",
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"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE";
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};
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or
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qcom,ispif@fda0a000 {
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cell-index = <0>;
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compatible = "qcom,ispif-v3.0", "qcom,ispif";
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reg = <0xfda0a000 0x300>;
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reg-names = "ispif";
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interrupts = <0 55 0>;
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interrupt-names = "ispif";
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qcom,num-isps = <2>
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vdd-supply = <&gdsc_camss_top>;
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clocks = <&clock_mmss clk_camss_ispif_ahb_clk>,
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<&clock_mmss clk_csi0_clk_src>,
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<&clock_mmss clk_camss_csi0_clk>,
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<&clock_mmss clk_camss_csi0rdi_clk>,
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<&clock_mmss clk_camss_csi0pix_clk>,
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<&clock_mmss clk_csi1_clk_src>,
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<&clock_mmss clk_camss_csi1_clk>,
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<&clock_mmss clk_camss_csi1rdi_clk>,
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<&clock_mmss clk_camss_csi1pix_clk>,
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<&clock_mmss clk_csi2_clk_src>,
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<&clock_mmss clk_camss_csi2_clk>,
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<&clock_mmss clk_camss_csi2rdi_clk>,
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<&clock_mmss clk_camss_csi2pix_clk>,
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<&clock_mmss clk_csi3_clk_src>,
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<&clock_mmss clk_camss_csi3_clk>,
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<&clock_mmss clk_camss_csi3rdi_clk>,
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<&clock_mmss clk_camss_csi3pix_clk>,
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<&clock_mmss clk_vfe0_clk_src>,
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<&clock_mmss clk_camss_vfe0_clk>,
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<&clock_mmss clk_camss_csi_vfe0_clk>,
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<&clock_mmss clk_vfe1_clk_src>,
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<&clock_mmss clk_camss_vfe1_clk>,
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<&clock_mmss clk_camss_csi_vfe1_clk>;
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clock-names = "ispif_ahb_clk",
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"csi0_src_clk", "csi0_clk",
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"csi0_pix_clk", "csi0_rdi_clk",
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"csi1_src_clk", "csi1_clk",
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"csi1_pix_clk", "csi1_rdi_clk",
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"csi2_src_clk", "csi2_clk",
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"csi2_pix_clk", "csi2_rdi_clk",
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"csi3_src_clk", "csi3_clk",
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"csi3_pix_clk", "csi3_rdi_clk",
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"vfe0_clk_src", "camss_vfe_vfe0_clk", "camss_csi_vfe0_clk",
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"vfe1_clk_src", "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";
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qcom,clock-rates = <0
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200000000 0 0 0
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200000000 0 0 0
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200000000 0 0 0
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200000000 0 0 0
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0 0 0
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0 0 0>;
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qcom,clock-control = "NO_SET_RATE",
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"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE",
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"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE";
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};
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