792 lines
35 KiB
Plaintext
792 lines
35 KiB
Plaintext
Qualcomm MDSS MDP
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MDSS is Mobile Display SubSystem which implements Linux framebuffer APIs to
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drive user interface to different panel interfaces. MDP driver is the core of
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MDSS which manage all data paths to different panel interfaces.
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Required properties
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- compatible : Must be "qcom,mdss_mdp"
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- "qcom,mdss_mdp3" for mdp3
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- reg : offset and length of the register set for the device.
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- reg-names : names to refer to register sets related to this device
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- interrupts : Interrupt associated with MDSS.
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- vdd-supply : Phandle for vdd regulator device node.
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- qcom,max-clk-rate: Specify maximum MDP core clock rate in hz that this
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device supports.
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- qcom,mdss-pipe-vig-off: Array of offset for MDP source surface pipes of
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type VIG, the offsets are calculated from
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register "mdp_phys" defined in reg property.
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The number of offsets defined here should
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reflect the amount of VIG pipes that can be
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active in MDP for this configuration.
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- qcom,mdss-pipe-vig-fetch-id: Array of shared memory pool fetch ids
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corresponding to the VIG pipe offsets defined in
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previous property, the amount of fetch ids
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-vig-off
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- qcom,mdss-pipe-vig-xin-id: Array of VBIF clients ids (xins) corresponding
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to the respective VIG pipes. Number of xin ids
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-vig-off
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- qcom,mdss-pipe-vig-clk-ctrl-off: Array of offsets describing clk control
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offsets for dynamic clock gating. 1st value
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in the array represents offset of the control
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register. 2nd value represents bit offset within
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control register and 3rd value represents bit
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offset within status register. Number of tuples
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-vig-off
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- qcom,mdss-pipe-rgb-off: Array of offsets for MDP source surface pipes of
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type RGB, the offsets are calculated from
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register "mdp_phys" defined in reg property.
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The number of offsets defined here should
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reflect the amount of RGB pipes that can be
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active in MDP for this configuration.
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- qcom,mdss-pipe-rgb-fetch-id: Array of shared memory pool fetch ids
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corresponding to the RGB pipe offsets defined in
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previous property, the amount of fetch ids
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-rgb-off
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- qcom,mdss-pipe-rgb-xin-id: Array of VBIF clients ids (xins) corresponding
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to the respective RGB pipes. Number of xin ids
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-rgb-off
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- qcom,mdss-pipe-rgb-clk-ctrl-off: Array of offsets describing clk control
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offsets for dynamic clock gating. 1st value
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in the array represents offset of the control
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register. 2nd value represents bit offset within
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control register and 3rd value represents bit
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offset within status register. Number of tuples
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-rgb-off
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- qcom,mdss-pipe-dma-off: Array of offsets for MDP source surface pipes of
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type DMA, the offsets are calculated from
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register "mdp_phys" defined in reg property.
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The number of offsets defined here should
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reflect the amount of DMA pipes that can be
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active in MDP for this configuration.
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- qcom,mdss-pipe-dma-fetch-id: Array of shared memory pool fetch ids
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corresponding to the DMA pipe offsets defined in
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previous property, the amount of fetch ids
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-dma-off
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- qcom,mdss-pipe-dma-xin-id: Array of VBIF clients ids (xins) corresponding
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to the respective DMA pipes. Number of xin ids
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-dma-off
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- qcom,mdss-pipe-dma-clk-ctrl-off: Array of offsets describing clk control
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offsets for dynamic clock gating. 1st value
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in the array represents offset of the control
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register. 2nd value represents bit offset within
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control register and 3rd value represents bit
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offset within status register. Number of tuples
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-dma-off
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- qcom,mdss-pipe-cursor-off: Array of offsets for MDP source surface pipes of
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type cursor, the offsets are calculated from
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register "mdp_phys" defined in reg property.
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The number of offsets defined here should
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reflect the amount of cursor pipes that can be
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active in MDP for this configuration. Meant for
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hardware that has hw cursors support as a
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source pipe.
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- qcom,mdss-pipe-cursor-xin-id: Array of VBIF clients ids (xins) corresponding
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to the respective cursor pipes. Number of xin ids
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-cursor-off
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- qcom,mdss-pipe-cursor-clk-ctrl-off: Array of offsets describing clk control
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offsets for dynamic clock gating. 1st value
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in the array represents offset of the control
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register. 2nd value represents bit offset within
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control register and 3rd value represents bit
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offset within status register. Number of tuples
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-cursor-off
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- qcom,mdss-ctl-off: Array of offset addresses for the available ctl
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hw blocks within MDP, these offsets are
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calculated from register "mdp_phys" defined in
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reg property. The number of ctl offsets defined
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here should reflect the number of control paths
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that can be configured concurrently on MDP for
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this configuration.
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- qcom,mdss-wb-off: Array of offset addresses for the progammable
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writeback blocks within MDP. The number of
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offsets defined should match the number of ctl
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blocks defined in property: qcom,mdss-ctl-off
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- qcom,mdss-mixer-intf-off: Array of offset addresses for the available
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mixer blocks that can drive data to panel
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interfaces.
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These offsets are be calculated from register
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"mdp_phys" defined in reg property.
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The number of offsets defined should reflect the
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amount of mixers that can drive data to a panel
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interface.
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- qcom,mdss-dspp-off: Array of offset addresses for the available dspp
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blocks. These offsets are calculated from
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regsiter "mdp_phys" defined in reg property.
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The number of dspp blocks should match the
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number of mixers driving data to interface
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defined in property: qcom,mdss-mixer-intf-off
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- qcom,mdss-pingpong-off: Array of offset addresses for the available
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pingpong blocks. These offsets are calculated
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from regsiter "mdp_phys" defined in reg property.
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The number of pingpong blocks should match the
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number of mixers driving data to interface
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defined in property: qcom,mdss-mixer-intf-off
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- qcom,mdss-mixer-wb-off: Array of offset addresses for the available
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mixer blocks that can be drive data to writeback
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block. These offsets will be calculated from
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register "mdp_phys" defined in reg property.
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The number of writeback mixer offsets defined
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should reflect the number of mixers that can
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drive data to a writeback block.
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- qcom,mdss-intf-off: Array of offset addresses for the available MDP
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video interface blocks that can drive data to a
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panel controller through timing engine.
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The offsets are calculated from "mdp_phys"
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defined in reg property. The number of offsets
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defiend should reflect the number of progammable
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interface blocks available in hardware.
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- qcom,mdss-pref-prim-intf: A string which indicates the configured hardware
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interface between MDP and the primary panel.
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Individual panel controller drivers initialize
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hardware based on this property.
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Based on the interfaces supported at present,
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possible values are:
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- "dsi"
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- "edp"
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- "hdmi"
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Bus Scaling Data:
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- qcom,msm-bus,name: String property describing MDSS client.
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- qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases
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defined in the vectors property. This must be
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set to <3> for MDSS driver where use-case 0 is
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used to take off MDSS BW votes from the system.
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And use-case 1 & 2 are used in ping-pong fashion
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to generate run-time BW requests.
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- qcom,msm-bus,active-only: A boolean flag indicating if it is active only.
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- qcom,msm-bus,num-paths: This represents the number of paths in each
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Bus Scaling Usecase. This value depends on
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how many number of AXI master ports are
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dedicated to MDSS for particular chipset. This
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value represents the RT + NRT AXI master ports.
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- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format
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of (src, dst, ab, ib) which is defined at
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Documentation/devicetree/bindings/arm/msm/msm_bus.txt
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* Current values of src & dst are defined at
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include/linux/msm-bus-board.h
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src values allowed for MDSS are:
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22 = MSM_BUS_MASTER_MDP_PORT0
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23 = MSM_BUS_MASTER_MDP_PORT1
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25 = MSM_BUS_MASTER_ROTATOR
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dst values allowed for MDSS are:
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512 = MSM_BUS_SLAVE_EBI_CH0
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ab: Represents aggregated bandwidth.
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ib: Represents instantaneous bandwidth.
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* Total number of 4 cell properties will be
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(number of use-cases * number of paths).
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* These values will be overridden by the driver
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based on the run-time requirements. So initial
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ab and ib values defined here are random and
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bare no logic except for the use-case 0 where ab
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and ib values needs to be 0.
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* Define realtime vector properties followed by
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non-realtime vector properties.
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- qcom,mdss-prefill-outstanding-buffer-bytes: The size of mdp outstanding buffer
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in bytes. The buffer is filled during prefill
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time and the buffer size shall be included in
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prefill bandwidth calculation.
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- qcom,mdss-prefill-y-buffer-bytes: The size of mdp y plane buffer in bytes. The
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buffer is filled during prefill time when format
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is YUV and the buffer size shall be included in
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prefill bandwidth calculation.
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- qcom,mdss-prefill-scaler-buffer-lines-bilinear: The value indicates how many lines
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of scaler line buffer need to be filled during
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prefill time. If bilinear scalar is enabled, then this
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number of lines is used to determine how many bytes
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of scaler buffer to be included in prefill bandwidth
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calculation.
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- qcom,mdss-prefill-scaler-buffer-lines-caf: The value indicates how many lines of
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of scaler line buffer need to be filled during
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prefill time. If CAF mode filter is enabled, then
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this number of lines is used to determine how many
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bytes of scaler buffer to be included in prefill
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bandwidth calculation.
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- qcom,mdss-prefill-post-scaler-buffer: The size of post scaler buffer in bytes.
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The buffer is used to smooth the output of the
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scaler. If the buffer is present in h/w, it is
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filled during prefill time and the number of bytes
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shall be included in prefill bandwidth calculation.
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- qcom,mdss-prefill-pingpong-buffer-pixels: The size of pingpong buffer in pixels.
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The buffer is used to keep pixels flowing to the
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panel interface. If the vertical start position of a
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layer is in the beginning of the active area, pingpong
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buffer must be filled during prefill time to generate
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starting lines. The number of bytes to be filled is
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determined by the line width, starting position,
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byte per pixel and scaling ratio, this number shall be
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included in prefill bandwidth calculation.
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- qcom,mdss-prefill-fbc-lines: The value indicates how many lines are required to fill
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fbc buffer during prefill time if FBC (Frame Buffer
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Compressor) is enabled. The number of bytes to be filled
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is determined by the line width, bytes per pixel and
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scaling ratio, this number shall be included in prefill bandwidth
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calculation.
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- qcom,max-mixer-width: Specify maximum MDP mixer width that the device supports.
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This is a mandatory property, if not specified then
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mdp probe will fail.
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Optional properties:
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- batfet-supply : Phandle for battery FET regulator device node.
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- vdd-cx-supply : Phandle for vdd CX regulator device node.
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- qcom,vbif-settings : Array with key-value pairs of constant VBIF register
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settings used to setup MDSS QoS for optimum performance.
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The key used should be offset from "vbif_phys" register
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defined in reg property.
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- qcom,vbif-nrt-settings : The key used should be offset from "vbif_nrt_phys"
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register defined in reg property. Refer qcom,vbif-settings
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for a detailed description of this binding.
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- qcom,mdp-settings : Array with key-value pairs of constant MDP register
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settings used to setup MDSS QoS for best performance.
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The key used should be offset from "mdp_phys" register
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defined in reg property.
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- qcom,mdss-smp-data: Array of shared memory pool data for dynamic SMP. There
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should be only two values in this property. The first
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value corresponds to the number of smp blocks and the
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second is the size of each block present in the mdss
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hardware. This property is optional for MDP hardware
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with fix pixel latency ram.
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- qcom,mdss-rot-block-size: The size of a memory block (in pixels) to be used
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by the rotator. If this property is not specified,
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then a default value of 128 pixels would be used.
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- qcom,mdss-has-bwc: Boolean property to indicate the presence of bandwidth
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compression feature in the rotator.
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- qcom,mdss-has-non-scalar-rgb: Boolean property to indicate the presence of RGB
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pipes which have no scaling support.
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- qcom,mdss-has-decimation: Boolean property to indicate the presence of
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decimation feature in fetch.
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- qcom,mdss-has-fixed-qos-arbiter-enabled: Boolean property to indicate the
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presence of rt/nrt feature. This feature enables
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increased performance by prioritizing the real time
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(rt) traffic over non real time (nrt) traffic to
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access the memory.
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- qcom,mdss-num-nrt-paths: Integer property represents the number of non-realtime
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paths in each Bus Scaling Usecase. This value depends on
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number of AXI ports are dedicated to non-realtime VBIF for
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particular chipset. This property is mandatory when
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"qcom,mdss-has-fixed-qos-arbiter-enabled" is enabled.
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These paths must be defined after rt-paths in
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"qcom,msm-bus,vectors-KBps" vector request.
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- qcom,mdss-has-source-split: Boolean property to indicate if source split
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feature is available or not.
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- qcom,mdss-has-rotator-downscale: Boolean property to indicate if rotator
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downscale feature is available or not.
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- qcom,mdss-ad-off: Array of offset addresses for the available
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Assertive Display (AD) blocks. These offsets
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are calculated from the register "mdp_phys"
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defined in reg property. The number of AD
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offsets should be less than or equal to the
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number of mixers driving interfaces defined in
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property: qcom,mdss-mixer-intf-off. Assumes
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that AD blocks are aligned with the mixer
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offsets as well (i.e. the first mixer offset
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corresponds to the same pathway as the first
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AD offset).
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- qcom,mdss-has-wb-ad: Boolean property to indicate assertive display feature
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support on write back framebuffer.
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- qcom,mdss-no-lut-read: Boolean property to indicate reading of LUT is
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not supported.
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- qcom,mdss-no-hist-vote Boolean property to indicate histogram reads
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and histogram LUT writes do not need additional
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bandwidth voting.
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- qcom,mdss-mdp-wfd-mode: A string that specifies what is the mode of
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writeback wfd block.
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"intf" = Writeback wfd block is
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connected to the interface mixer.
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"shared" = Writeback block shared
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between wfd and rotator.
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"dedicated" = Dedicated writeback
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block for wfd using writeback mixer.
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- qcom,mdss-smp-mb-per-pipe: Maximum number of shared memory pool blocks
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restricted for a source surface pipe. If this
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property is not specified, no such restriction
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would be applied.
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- qcom,mdss-highest-bank-bit: Property to indicate tile format as opposed to usual
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linear format. The value tells the GPU highest memory
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bank bit used.
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- qcom,mdss-pipe-rgb-fixed-mmb: Array of indexes describing fixed Memory Macro
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Blocks (MMBs) for rgb pipes. First value denotes
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total numbers of MMBs per pipe while values, if
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any, following first one denotes indexes of MMBs
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to that RGB pipe.
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- qcom,mdss-pipe-vig-fixed-mmb: Array of indexes describing fixed Memory Macro
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Blocks (MMBs) for vig pipes. First value denotes
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total numbers of MMBs per pipe while values, if
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any, following first one denotes indexes of MMBs
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to that VIG pipe.
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- qcom,mdss-pipe-sw-reset-off: Property to indicate offset to the register which
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holds sw_reset bitmap for different MDSS
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components.
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- qcom,mdss-pipe-vig-sw-reset-map: Array of bit offsets for vig pipes within
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sw_reset register bitmap. Number of offsets
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-vig-off
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- qcom,mdss-pipe-rgb-sw-reset-map: Array of bit offsets for rgb pipes within
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sw_reset register bitmap. Number of offsets
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-rgb-off
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- qcom,mdss-pipe-dma-sw-reset-map: Array of bit offsets for dma pipes within
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sw_reset register bitmap. Number of offsets
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defined should match the number of offsets
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defined in property: qcom,mdss-pipe-dma-off
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- qcom,mdss-default-ot-wr-limit: This integer value indicates maximum number of pending
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writes that can be allowed on each WR xin.
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This value can be used to reduce the pending writes
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limit and can be tuned to match performance
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requirements depending upon system state.
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Some platforms require a dynamic ot limiting in
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some cases. Setting this default ot write limit
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will enable this dynamic limiting for the write
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operations in the platforms that require these
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limits.
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- qcom,mdss-default-ot-rd-limit: This integer value indicates the default number of pending
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reads that can be allowed on each RD xin.
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Some platforms require a dynamic ot limiting in
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some cases. Setting this default ot read limit
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will enable this dynamic limiting for the read
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operations in the platforms that require these
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limits.
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- qcom,mdss-clk-levels: This array indicates the mdp core clock level selection
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array. Core clock is calculated for each frame and
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hence depending upon calculated value, clock rate
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will be rounded up to the next level according to
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this table. Order of entries need to be ordered in
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ascending order.
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- qcom,mdss-vbif-qos-rt-setting: This array is used to program vbif qos remapper register
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priority for real time clients.
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- qcom,mdss-vbif-qos-nrt-setting: This array is used to program vbif qos remapper register
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priority for non real time clients.
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- qcom,mdss-traffic-shaper-enabled: This boolean property enables traffic shaper functionality
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for MDSS rotator which spread out rotator bandwidth request
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so that rotator don't compete with other real time read
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clients.
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- qcom,mdss-dram-channels: This represents the number of channels in the
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Bus memory controller.
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- qcom,regs-dump-mdp: This array represents the registers offsets that
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will be dumped from the mdp when the debug logging
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is enabled; each entry in the table is an start and
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end offset from the MDP addres "mdp_phys", the
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format of each entry is as follows:
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<start_offset end_offset>
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Ex:
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<0x01000 0x01404>
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Will dump the MDP registers
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from the address: "mdp_phys + 0x01000"
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to the address: "mdp_phys + 0x01404"
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- qcom,regs-dump-names-mdp: This array represents the tag that will be used
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for each of the entries defined within regs-dump.
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Note that each tag matches with one of the
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regs-dump entries in the same order as they
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are defined.
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Fudge Factors: Fudge factors are used to boost demand for
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resources like bus bandswidth, clk rate etc. to
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overcome system inefficiencies and avoid any
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glitches. These fudge factors are expressed in
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terms of numerator and denominator. First value
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is numerator followed by denominator. They all
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are optional but highly recommended.
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Ex:
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x = value to be fudged
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a = numerator, default value is 1
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b = denominator, default value is 1
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FUDGE(x, a, b) = ((x * a) / b)
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- qcom,mdss-ib-factor: This fudge factor is applied to calculated ib
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values in default conditions.
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- qcom,mdss-ib-factor-overlap: This fudge factor is applied to calculated ib
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values when the overlap bandwidth is the
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predominant value compared to prefill bandwidth
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value.
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- qcom,mdss-clk-factor: This fudge factor is applied to calculated mdp
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clk rate in default conditions.
|
|
|
|
- qcom,max-bandwidth-low-kbps: This value indicates the max bandwidth in KB
|
|
that can be supported without underflow.
|
|
This is a low bandwidth threshold which should
|
|
be applied in most scenarios to be safe from
|
|
underflows when unable to satisfy bandwith
|
|
requirements.
|
|
- qcom,max-bandwidth-high-kbps: This value indicates the max bandwidth in KB
|
|
that can be supported without underflow.
|
|
This is a high bandwidth threshold which can be
|
|
applied in scenarios where panel interface can
|
|
be more tolerant to memory latency such as
|
|
command mode panels.
|
|
- qcom,max-bandwidth-per-pipe-kbps: A two dimensional array indicating the max
|
|
bandwidth in KB that a single pipe can support
|
|
without underflow for various usecases. The
|
|
first parameter indicates the usecase and the
|
|
second parameter gives the max bw allowed for
|
|
the usecase. Following are the enum values for
|
|
modes in different cases:
|
|
For default case, mode = 1
|
|
camera usecase, mode = 2
|
|
hflip usecase, mode = 4
|
|
vflip usecase, mode = 8
|
|
First parameter/mode value need to match enum,
|
|
mdss_mdp_max_bw_mode, present in
|
|
include/uapi/linux/msm_mdp.h.
|
|
- qcom,max-bw-settings: This two dimension array indicates the max bandwidth
|
|
in KB that has to be supported when particular
|
|
scenarios are involved such as camera, flip.
|
|
The first parameter indicate the
|
|
scenario/usecase and second paramter indicate
|
|
the maximum bandwidth for that usecase.
|
|
Following are the enum values for modes in different
|
|
cases:
|
|
For default case, mode = 1
|
|
camera usecase, mode = 2
|
|
hflip usecase, mode = 4
|
|
vflip usecase, mode = 8
|
|
First parameter/mode value need to match enum,
|
|
mdss_mdp_max_bw_mode, present in
|
|
include/uapi/linux/msm_mdp.h.
|
|
|
|
- qcom,mdss-has-panic-ctrl: Boolean property to indicate if panic/robust signal
|
|
control feature is available or not.
|
|
- qcom,mdss-en-svs-high: Boolean property to indicate if this target needs to
|
|
enable the svs high voltage level for CX rail.
|
|
- qcom,mdss-pipe-vig-panic-ctrl-offsets: Array of panic/robust signal offsets
|
|
corresponding to the respective VIG pipes.
|
|
Number of signal offsets should match the
|
|
number of offsets defined in property:
|
|
qcom,mdss-pipe-vig-off
|
|
- qcom,mdss-pipe-rgb-panic-ctrl-offsets: Array of panic/robust signal offsets
|
|
corresponding to the respective RGB pipes.
|
|
Number of signal offsets should match the
|
|
number of offsets defined in property:
|
|
qcom,mdss-pipe-rgb-off
|
|
- qcom,mdss-pipe-dma-panic-ctrl-offsets: Array of panic/robust signal offsets
|
|
corresponding to the respective DMA pipes.
|
|
Number of signal offsets should match the
|
|
number of offsets defined in property:
|
|
qcom,mdss-pipe-dma-off
|
|
- qcom,mdss-per-pipe-panic-luts: Array to configure the panic/robust luts for
|
|
each rt and nrt clients. This property is
|
|
for the MDPv1.7 and above, which configures
|
|
the panic independently on each client.
|
|
Each element of the array corresponds to:
|
|
First element - panic for linear formats
|
|
Second element - panic for tile formats
|
|
Third element - robust for linear formats
|
|
Fourth element - robust for tile formats
|
|
- qcom,mdss-has-pingpong-split: Boolean property to indicate if destination
|
|
split feature is available or not in the target.
|
|
- qcom,mdss-slave-pingpong-off: Offset address for the extra TE block which needs
|
|
to be programmed when pingpong split feature is enabled.
|
|
Offset is calculated from the "mdp_phys"
|
|
register value. Mandatory when qcom,mdss-has-pingpong-split
|
|
is enabled.
|
|
- qcom,mdss-ppb-off: Array of offset addresses of ping pong buffer control registers.
|
|
The offsets are calculated from the "mdp_phys" base address
|
|
specified. The number of offsets should match the
|
|
number of ping pong buffers available in the hardware.
|
|
Mandatory when qcom,mdss-has-pingpong-split is enabled.
|
|
- qcom,mdss-cdm-off: Array of offset addresses for the available
|
|
chroma down modules that can convert RGB data
|
|
to YUV before sending it to the interface
|
|
block. These offsets will be calculated from
|
|
register "mdp_phys" define in reg property. The
|
|
number of cdm offsets should reflect the number
|
|
of cdm blocks present in hardware.
|
|
- qcom,mdss-dsc-off: Array of offset addresses for the available
|
|
display stream compression module block.
|
|
These offsets will be calculated from
|
|
register "mdp_phys" define in reg property. The
|
|
number of dsc offsets should reflect the number
|
|
of dsc blocks present in hardware.
|
|
- qcom,max-pipe-width: This value specifies the maximum MDP SSPP width
|
|
the device supports. If not specified, a default value
|
|
of 2048 will be applied.
|
|
|
|
Optional subnodes:
|
|
- mdss_fb: Child nodes representing the frame buffer virtual devices.
|
|
|
|
Subnode properties:
|
|
- compatible : Must be "qcom,mdss-fb"
|
|
- cell-index : Index representing frame buffer
|
|
- qcom,mdss-mixer-swap: A boolean property that indicates if the mixer muxes
|
|
need to be swapped based on the target panel.
|
|
By default the property is not defined.
|
|
- qcom,memblock-reserve: Specifies the memory location and the size reserved
|
|
for the framebuffer used to display the splash screen.
|
|
This property is required whenever the continuous splash
|
|
screen feature is enabled for the corresponding
|
|
framebuffer device. It should be used for only 32bit
|
|
kernel.
|
|
- qcom,cont-splash-memory: Specifies the memory block region reserved for
|
|
continuous splash screen feature. This property should be
|
|
defined for corresponding framebuffer device if
|
|
"qcom,memblock-reserve" is not defined when continuous
|
|
splash screen feature is enabled.
|
|
- linux,contiguous-region: Phandle to the continuous memory region reserved for
|
|
frame-buffer or continuous splash screen. Size of this
|
|
region is dependent on the display panel resolution and
|
|
buffering scheme for frame-buffer node. Currently driver
|
|
uses double buffering.
|
|
|
|
Example: Width = 1920, Height = 1080, BytesPerPixel = 4,
|
|
Number of frame-buffers reserved = 2.
|
|
Size = 1920*1080*4*2 = ROUND_1MB(15.8MB) = 16MB.
|
|
- qcom,mdss-fb-splash-logo-enabled: The boolean entry enables the framebuffer
|
|
driver to display the splash logo image.
|
|
It is independent of continuous splash
|
|
screen feature and has no relation with
|
|
qcom,cont-splash-enabled entry present in
|
|
panel configuration.
|
|
- qcom,mdss-idle-power-collapse-enabled: Boolean property that enables support
|
|
for mdss power collapse in idle
|
|
screen use cases with smart panels.
|
|
- qcom,boot-indication-enabled: Boolean property that enables turning on the blue
|
|
LED for notifying that the device is in boot
|
|
process.
|
|
|
|
- qcom,mdss-pp-offets: A node that lists the offsets of post processing blocks
|
|
from base module.
|
|
-- qcom,mdss-mdss-sspp-igc-lut-off: This 32 bit value provides the
|
|
offset to the IGC lut rams from mdp_phys base.
|
|
-- qcom,mdss-sspp-vig-pcc-off: This 32 bit value provides the offset
|
|
to PCC block from the VIG pipe base address.
|
|
-- qcom,mdss-sspp-rgb-pcc-off: This 32 bit value provides the offset
|
|
to PCC block from the RGB pipe base address.
|
|
-- qcom,mdss-sspp-dma-pcc-off: This 32 bit value provides the offset
|
|
to PCC block from the DMA pipe base address.
|
|
-- qcom,mdss-dspp-pcc-off: This 32 bit value provides the offset
|
|
to PCC block from the DSPP pipe base address.
|
|
-- qcom,mdss-lm-pgc-off: This 32 bit value provides the offset
|
|
to PGC block from the layer mixer base address.
|
|
-- qcom,mdss-dspp-gamut-off: This 32 bit value provides the offset
|
|
to gamut block from DSPP base address.
|
|
-- qcom,mdss-dspp-pgc-off: This 32 bit value provides the offset to
|
|
PGC block from the DSPP base address.
|
|
|
|
- smmu_mdp_***: Child nodes representing the mdss smmu virtual devices.
|
|
Mandatory smmu v2 and not required for smmu v1.
|
|
|
|
Subnode properties:
|
|
- compatible : Compatible name used in smmu v2.
|
|
smmu_v2 names should be:
|
|
"qcom,smmu_mdp_unsec" - smmu context bank device for
|
|
unsecure mdp domain.
|
|
"qcom,smmu_rot_unsec" - smmu context bank device for
|
|
unsecure rotation domain.
|
|
"qcom,smmu_mdp_sec" - smmu context bank device for
|
|
secure mdp domain.
|
|
"qcom,smmu_rot_sec" - smmu context bank device for
|
|
secure rotation domain.
|
|
"qcom,smmu_arm_mdp_unsec" - arm smmu context bank device for
|
|
unsecure mdp domain.
|
|
"qcom,smmu_arm_mdp_sec" - arm smmu context bank device for
|
|
secure mdp domain.
|
|
- gdsc-mmagic-mdss-supply: Phandle for mmagic mdss supply regulator device node.
|
|
- clocks: List of Phandles for clock device nodes
|
|
needed by the device.
|
|
- clock-names: List of clock names needed by the device.
|
|
|
|
Subnode properties:
|
|
Required properties:
|
|
- compatible: Must be "qcom,mdss_wb"
|
|
- qcom,mdss_pan_res: Array containing two elements, width and height which
|
|
specifies size of writeback buffer.
|
|
- qcom,mdss_pan_bpp: Specifies bits per pixel for writeback buffer.
|
|
- qcom,mdss-fb-map: Specifies the handle for frame buffer.
|
|
|
|
Example:
|
|
mdss_mdp: qcom,mdss_mdp@fd900000 {
|
|
compatible = "qcom,mdss_mdp";
|
|
reg = <0xfd900000 0x22100>,
|
|
<0xfd924000 0x1000>,
|
|
<0xfd925000 0x1000>;
|
|
reg-names = "mdp_phys", "vbif_phys", "vbif_nrt_phys";
|
|
interrupts = <0 72 0>;
|
|
vdd-supply = <&gdsc_mdss>;
|
|
batfet-supply = <&pm8941_chg_batif>;
|
|
vdd-cx-supply = <&pm8841_s2_corner>;
|
|
|
|
/* Bus Scale Settings */
|
|
qcom,msm-bus,name = "mdss_mdp";
|
|
qcom,msm-bus,num-cases = <3>;
|
|
qcom,msm-bus,num-paths = <2>;
|
|
qcom,mdss-dram-channels = <2>;
|
|
qcom,mdss-num-nrt-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<22 512 0 0>, <23 512 0 0>,
|
|
<22 512 0 6400000>, <23 512 0 6400000>,
|
|
<22 512 0 6400000>, <23 512 0 6400000>;
|
|
|
|
/* Fudge factors */
|
|
qcom,mdss-ab-factor = <2 1>; /* 2 times */
|
|
qcom,mdss-ib-factor = <3 2>; /* 1.5 times */
|
|
qcom,mdss-high-ib-factor = <2 1>; /* 2 times */
|
|
qcom,mdss-clk-factor = <5 4>; /* 1.25 times */
|
|
|
|
/* Clock levels */
|
|
qcom,mdss-clk-levels = <92310000, 177780000, 200000000>;
|
|
|
|
/* VBIF QoS remapper settings*/
|
|
qcom,mdss-vbif-qos-rt-setting = <2 2 2 2>;
|
|
qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>;
|
|
|
|
qcom,max-bandwidth-low-kbps = <2300000>;
|
|
qcom,max-bandwidth-high-kbps = <3000000>;
|
|
qcom,max-bandwidth-per-pipe-kbps = <4 2100000>,
|
|
<8 1800000>;
|
|
qcom,max-bw-settings = <1 2300000>,
|
|
<2 1700000>,
|
|
<4 2300000>,
|
|
<8 2000000>;
|
|
|
|
qcom,max-mixer-width = <2048>;
|
|
qcom,max-pipe-width = <2048>;
|
|
qcom,max-clk-rate = <320000000>;
|
|
qcom,vbif-settings = <0x0004 0x00000001>,
|
|
<0x00D8 0x00000707>;
|
|
qcom,vbif-nrt-settings = <0x0004 0x00000001>,
|
|
<0x00D8 0x00000707>;
|
|
qcom,mdp-settings = <0x02E0 0x000000AA>,
|
|
<0x02E4 0x00000055>;
|
|
qcom,mdss-pipe-vig-off = <0x00001200 0x00001600
|
|
0x00001A00>;
|
|
qcom,mdss-pipe-rgb-off = <0x00001E00 0x00002200
|
|
0x00002600>;
|
|
qcom,mdss-pipe-dma-off = <0x00002A00 0x00002E00>;
|
|
qcom,mdss-pipe-cursor-off = <0x00035000 0x00037000>;
|
|
qcom,mdss-dsc-off = <0x00081000 0x00081400>;
|
|
qcom,mdss-pipe-vig-fetch-id = <1 4 7>;
|
|
qcom,mdss-pipe-rgb-fetch-id = <16 17 18>;
|
|
qcom,mdss-pipe-dma-fetch-id = <10 13>;
|
|
qcom,mdss-pipe-rgb-fixed-mmb = <2 0 1>,
|
|
<2 2 3>,
|
|
<2 4 5>,
|
|
<2 6 7>;
|
|
qcom,mdss-pipe-vig-fixed-mmb = <1 8>,
|
|
<1 9>,
|
|
<1 10>,
|
|
<1 11>;
|
|
qcom,mdss-smp-data = <22 4096>;
|
|
qcom,mdss-rot-block-size = <64>;
|
|
qcom,mdss-rotator-ot-limit = <2>;
|
|
qcom,mdss-smp-mb-per-pipe = <2>;
|
|
qcom,mdss-pref-prim-intf = "dsi";
|
|
qcom,mdss-has-non-scalar-rgb;
|
|
qcom,mdss-has-bwc;
|
|
qcom,mdss-has-decimation;
|
|
qcom,mdss-has-fixed-qos-arbiter-enabled;
|
|
qcom,mdss-has-source-split;
|
|
qcom,mdss-wfd-mode = "intf";
|
|
qcom,mdss-no-lut-read;
|
|
qcom,mdss-no-hist-vote;
|
|
qcom,mdss-traffic-shaper-enabled;
|
|
qcom,mdss-has-rotator-downscale;
|
|
|
|
qcom,mdss-has-pingpong-split;
|
|
qcom,mdss-pipe-vig-xin-id = <0 4 8>;
|
|
qcom,mdss-pipe-rgb-xin-id = <1 5 9>;
|
|
qcom,mdss-pipe-dma-xin-id = <2 10>;
|
|
qcom,mdss-pipe-cursor-xin-id = <7 7>;
|
|
|
|
qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x3AC 0 0>,
|
|
<0x3B4 0 0>,
|
|
<0x3BC 0 0>,
|
|
<0x3C4 0 0>;
|
|
|
|
qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x3AC 4 8>,
|
|
<0x3B4 4 8>,
|
|
<0x3BC 4 8>,
|
|
<0x3C4 4 8>;
|
|
|
|
qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x3AC 8 12>,
|
|
<0x3B4 8 12>;
|
|
|
|
qcom,mdss-per-pipe-panic-luts = <0x000f>,
|
|
<0xffff>,
|
|
<0xfffc>,
|
|
<0xff00>;
|
|
|
|
qcom,mdss-has-panic-ctrl;
|
|
qcom,mdss-pipe-vig-panic-ctrl-offsets = <0 1 2 3>;
|
|
qcom,mdss-pipe-rgb-panic-ctrl-offsets = <4 5 6 7>;
|
|
qcom,mdss-pipe-dma-panic-ctrl-offsets = <8 9>;
|
|
|
|
qcom,mdss-pipe-sw-reset-off = <0x0128>;
|
|
qcom,mdss-pipe-vig-sw-reset-map = <5 6 7 8>;
|
|
qcom,mdss-pipe-rgb-sw-reset-map = <9 10 11 12>;
|
|
qcom,mdss-pipe-dma-sw-reset-map = <13 14>;
|
|
|
|
qcom,mdss-ctl-off = <0x00000600 0x00000700 0x00000800
|
|
0x00000900 0x0000A00>;
|
|
qcom,mdss-mixer-intf-off = <0x00003200 0x00003600
|
|
0x00003A00>;
|
|
qcom,mdss-mixer-wb-off = <0x00003E00 0x00004200>;
|
|
qcom,mdss-dspp-off = <0x00004600 0x00004A00 0x00004E00>;
|
|
qcom,mdss-pingpong-off = <0x00012D00 0x00012E00 0x00012F00>;
|
|
qcom,mdss-wb-off = <0x00011100 0x00013100 0x00015100
|
|
0x00017100 0x00019100>;
|
|
qcom,mdss-intf-off = <0x00021100 0x00021300
|
|
0x00021500 0x00021700>;
|
|
qcom,mdss-cdm-off = <0x0007A200>;
|
|
qcom,mdss-ppb-off = <0x0000420>;
|
|
qcom,mdss-slave-pingpong-off = <0x00073000>
|
|
|
|
/* buffer parameters to calculate prefill bandwidth */
|
|
qcom,mdss-prefill-outstanding-buffer-bytes = <1024>;
|
|
qcom,mdss-prefill-y-buffer-bytes = <4096>;
|
|
qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>;
|
|
qcom,mdss-prefill-scaler-buffer-lines-caf = <4>;
|
|
qcom,mdss-prefill-post-scaler-buffer-pixels = <2048>;
|
|
qcom,mdss-prefill-pingpong-buffer-pixels = <5120>;
|
|
qcom,mdss-prefill-fbc-lines = <2>;
|
|
qcom,mdss-idle-power-collapse-enabled;
|
|
|
|
mdss_fb0: qcom,mdss_fb_primary {
|
|
cell-index = <0>;
|
|
compatible = "qcom,mdss-fb";
|
|
qcom,mdss-mixer-swap;
|
|
linux,contiguous-region = <&fb_mem>;
|
|
qcom,mdss-fb-splash-logo-enabled:
|
|
qcom,cont-splash-memory {
|
|
linux,contiguous-region = <&cont_splash_mem>;
|
|
};
|
|
};
|
|
|
|
qcom,mdss-pp-offsets {
|
|
qcom,mdss-sspp-mdss-igc-lut-off = <0x3000>;
|
|
qcom,mdss-sspp-vig-pcc-off = <0x1580>;
|
|
qcom,mdss-sspp-rgb-pcc-off = <0x180>;
|
|
qcom,mdss-sspp-dma-pcc-off = <0x180>;
|
|
qcom,mdss-lm-pgc-off = <0x3C0>;
|
|
qcom,mdss-dspp-gamut-off = <0x1600>;
|
|
qcom,mdss-dspp-pcc-off = <0x1700>;
|
|
qcom,mdss-dspp-pgc-off = <0x17C0>;
|
|
};
|
|
|
|
smmu_mdp_sec: qcom,smmu_mdp_sec_cb {
|
|
compatible = "qcom,smmu_mdp_sec";
|
|
iommus = <&mdp_smmu 1>;
|
|
gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>;
|
|
clocks = <&clock_mmss clk_smmu_mdp_ahb_clk>,
|
|
<&clock_mmss clk_smmu_mdp_axi_clk>;
|
|
clock-names = "dummy_clk", "dummy_clk";
|
|
};
|
|
|
|
qcom,mdss_wb_panel {
|
|
compatible = "qcom,mdss_wb";
|
|
qcom,mdss_pan_res = <1280 720>;
|
|
qcom,mdss_pan_bpp = <24>;
|
|
qcom,mdss-fb-map = <&mdss_fb1>;
|
|
};
|
|
};
|
|
|