158 lines
4.3 KiB
Plaintext
158 lines
4.3 KiB
Plaintext
SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
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Currently Freescale powerpc chip C29X is embedded with SEC 6.
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SEC 6 device tree binding include:
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-SEC 6 Node
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-Job Ring Node
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-Full Example
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=====================================================================
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SEC 6 Node
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Description
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Node defines the base address of the SEC 6 block.
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This block specifies the address range of all global
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configuration registers for the SEC 6 block.
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For example, In C293, we could see three SEC 6 node.
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PROPERTIES
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,sec-v6.0".
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- fsl,sec-era
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Usage: optional
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Value type: <u32>
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Definition: A standard property. Define the 'ERA' of the SEC
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device.
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- #address-cells
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Usage: required
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Value type: <u32>
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Definition: A standard property. Defines the number of cells
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for representing physical addresses in child nodes.
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- #size-cells
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Usage: required
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Value type: <u32>
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Definition: A standard property. Defines the number of cells
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for representing the size of physical addresses in
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child nodes.
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical
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address and length of the SEC 6 configuration registers.
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- ranges
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical address
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range of the SEC 6.0 register space (-SNVS not included). A
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triplet that includes the child address, parent address, &
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length.
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Note: All other standard properties (see the ePAPR) are allowed
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but are optional.
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EXAMPLE
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crypto@a0000 {
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compatible = "fsl,sec-v6.0";
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fsl,sec-era = <6>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xa0000 0x20000>;
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ranges = <0 0xa0000 0x20000>;
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};
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=====================================================================
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Job Ring (JR) Node
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Child of the crypto node defines data processing interface to SEC 6
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across the peripheral bus for purposes of processing
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cryptographic descriptors. The specified address
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range can be made visible to one (or more) cores.
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The interrupt defined for this node is controlled within
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the address range of this node.
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,sec-v6.0-job-ring".
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: Specifies a two JR parameters: an offset from
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the parent physical address and the length the JR registers.
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- interrupts
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Usage: required
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Value type: <prop_encoded-array>
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Definition: Specifies the interrupts generated by this
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device. The value of the interrupts property
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consists of one interrupt specifier. The format
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of the specifier is defined by the binding document
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describing the node's interrupt parent.
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EXAMPLE
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jr@1000 {
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compatible = "fsl,sec-v6.0-job-ring";
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reg = <0x1000 0x1000>;
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interrupts = <49 2 0 0>;
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};
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===================================================================
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Full Example
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Since some chips may contain more than one SEC, the dtsi contains
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only the node contents, not the node itself. A chip using the SEC
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should include the dtsi inside each SEC node. Example:
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In qoriq-sec6.0.dtsi:
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compatible = "fsl,sec-v6.0";
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fsl,sec-era = <6>;
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#address-cells = <1>;
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#size-cells = <1>;
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jr@1000 {
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compatible = "fsl,sec-v6.0-job-ring",
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"fsl,sec-v5.2-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.4-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x1000 0x1000>;
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};
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jr@2000 {
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compatible = "fsl,sec-v6.0-job-ring",
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"fsl,sec-v5.2-job-ring",
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"fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.4-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x2000 0x1000>;
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};
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In the C293 device tree, we add the include of public property:
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crypto@a0000 {
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/include/ "qoriq-sec6.0.dtsi"
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}
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crypto@a0000 {
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reg = <0xa0000 0x20000>;
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ranges = <0 0xa0000 0x20000>;
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jr@1000 {
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interrupts = <49 2 0 0>;
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};
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jr@2000 {
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interrupts = <50 2 0 0>;
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};
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};
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