49 lines
1.7 KiB
Plaintext
49 lines
1.7 KiB
Plaintext
Binding for a type of quad channel digital frequency synthesizer found on
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certain STMicroelectronics consumer electronics SoC devices.
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This version contains a programmable PLL which can generate up to 216, 432
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or 660MHz (from a 30MHz oscillator input) as the input to the digital
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synthesizers.
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be:
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"st,stih416-quadfs216", "st,quadfs"
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"st,stih416-quadfs432", "st,quadfs"
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"st,stih416-quadfs660-E", "st,quadfs"
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"st,stih416-quadfs660-F", "st,quadfs"
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"st,stih407-quadfs660-C", "st,quadfs"
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"st,stih407-quadfs660-D", "st,quadfs"
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- #clock-cells : from common clock binding; shall be set to 1.
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- reg : A Base address and length of the register set.
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- clocks : from common clock binding
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- clock-output-names : From common clock binding. The block has 4
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clock outputs but not all of them in a specific instance
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have to be used in the SoC. If a clock name is left as
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an empty string then no clock will be created for the
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output associated with that string index. If fewer than
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4 strings are provided then no clocks will be created
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for the remaining outputs.
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Example:
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clockgen_e: clockgen-e@fd3208bc {
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#clock-cells = <1>;
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compatible = "st,stih416-quadfs660-E", "st,quadfs";
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reg = <0xfd3208bc 0xB0>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-pix-mdtp-0",
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"clk-m-pix-mdtp-1",
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"clk-m-pix-mdtp-2",
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"clk-m-mpelpc";
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};
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