39 lines
715 B
Plaintext
39 lines
715 B
Plaintext
* TI - MPU (Main Processor Unit) subsystem
|
|
|
|
The MPU subsystem contain one or several ARM cores
|
|
depending of the version.
|
|
The MPU contain CPUs, GIC, L2 cache and a local PRCM.
|
|
|
|
Required properties:
|
|
- compatible : Should be "ti,omap3-mpu" for OMAP3
|
|
Should be "ti,omap4-mpu" for OMAP4
|
|
Should be "ti,omap5-mpu" for OMAP5
|
|
- ti,hwmods: "mpu"
|
|
|
|
Optional properties:
|
|
- sram: Phandle to the ocmcram node
|
|
|
|
Examples:
|
|
|
|
- For an OMAP5 SMP system:
|
|
|
|
mpu {
|
|
compatible = "ti,omap5-mpu";
|
|
ti,hwmods = "mpu"
|
|
};
|
|
|
|
- For an OMAP4 SMP system:
|
|
|
|
mpu {
|
|
compatible = "ti,omap4-mpu";
|
|
ti,hwmods = "mpu";
|
|
};
|
|
|
|
|
|
- For an OMAP3 monocore system:
|
|
|
|
mpu {
|
|
compatible = "ti,omap3-mpu";
|
|
ti,hwmods = "mpu";
|
|
};
|