126 lines
4.0 KiB
Plaintext
126 lines
4.0 KiB
Plaintext
Qualcomm MSM Clock controller
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Qualcomm MSM Clock controller devices contain PLLs, root clock generators
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and other clocking hardware blocks that provide stable, low power clocking to
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hardware blocks on Qualcomm SOCs. The clock controller device node lists the
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power supplies needed to be scaled using the vdd_*-supply property.
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Minor differences between hardware revisions are handled in code by re-using
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the compatible string to indicate the revision.
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Required properties:
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- compatible: Must be one of following,
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"qcom,gcc-8916"
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"qcom,gcc-8936"
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"qcom,gcc-8909"
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"qcom,gcc-8992"
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"qcom,gcc-8994"
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"qcom,gcc-8994v2"
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"qcom,gcc-8952"
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"qcom,gcc-spm-8952"
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"qcom,gcc-fsm9010"
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"qcom,gcc-8996"
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"qcom,gcc-8996-v2"
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"qcom,gcc-8996-v3"
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"qcom,gcc-8937"
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"qcom,gcc-gold"
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"qcom,gcc-spm-8937"
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"qcom,gcc-titanium"
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"qcom,rpmcc-8994"
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"qcom,rpmcc-8992"
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"qcom,rpmcc-8916"
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"qcom,rpmcc-8936"
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"qcom,rpmcc-8909"
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"qcom,cc-debug-8916"
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"qcom,cc-debug-8936"
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"qcom,cc-debug-8909"
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"qcom,cc-debug-8992"
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"qcom,cc-debug-8994"
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"qcom,cc-debug-8952"
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"qcom,cc-debug-titanium"
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"qcom,cc-debug-fsm9010"
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"qcom,cc-debug-8996"
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"qcom,cc-debug-8996-v2"
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"qcom,cc-debug-8996-v3"
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"qcom,cc-debug-8937"
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"qcom,cc-debug-gold"
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"qcom,gcc-mdss-8936"
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"qcom,gcc-mdss-8909"
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"qcom,gcc-mdss-8916"
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"qcom,gcc-mdss-8952"
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"qcom,gcc-mdss-8937"
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"qcom,gcc-mdss-gold"
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"qcom,gcc-mdss-titanium"
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"qcom,mmsscc-8994v2"
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"qcom,mmsscc-8994"
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"qcom,mmsscc-8992"
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"qcom,mmsscc-8996"
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"qcom,mmsscc-8996-v2"
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"qcom,mmsscc-8996-v3"
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"qcom,gpucc-8996"
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"qcom,gpucc-8996-v2"
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"qcom,gpucc-8996-v3"
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"qcom,gpucc-8996-v3.0"
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"qcom,gcc-gfx-titanium"
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"qcom,gcc-californium"
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"qcom,cc-debug-californium"
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"qcom,gcc-mdm9607"
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"qcom,cc-debug-mdm9607"
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"qcom,gcc-cobalt"
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"qcom,cc-debug-cobalt"
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- reg: Pairs of physical base addresses and region sizes of
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memory mapped registers.
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- reg-names: Names of the bases for the above registers. Currently,
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there is one expected base: "cc_base". Optional
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reg-names are "apcs_base", "meas", "mmss_base",
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"lpass_base", "apcs_c0_base", "apcs_c1_base",
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"apcs_cci_base".
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Optional properties:
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- vdd_dig-supply: The digital logic rail supply.
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- <pll>_dig-supply: Some PLLs might have separate digital supply on some
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targets. These properties will be provided on those
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targets for specific PLLs.
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- <pll>_analog-supply: Some PLLs might have separate analog supply on some
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targets. These properties will be provided on those
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targets for specific PLLs.
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- vdd_gpu_mx-supply: MX rail supply for the GPU core.
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- #clock_cells: If this device will also be providing controllable
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clocks, the clock_cells property needs to be specified.
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This will allow the common clock device tree framework
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to recognize _this_ device node as a clock provider.
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- qcom,<clk>-corner-<vers>: List of frequency voltage pairs that the clock can
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operate at. Drivers can use the OPP library API to
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operate on the list of OPPs registered using these
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values.
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- qcom,<clk>-speedbinX: A table of frequency (Hz) to voltage (corner) mapping
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that represents the max frequency possible for each
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supported voltage level for the clock.
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'X' is the speed bin into which the device falls into -
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a bin will have unique frequency-voltage relationships.
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The value 'X' is read from efuse registers, and the right
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table is picked from multiple possible tables.
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- qcom,<clock-name>-opp-handle: phandle references to the devices for which OPP
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table is filled with the clock frequency and voltage
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values.
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- qcom,<clock-name>-opp-store-vcorner: phandle references to the devices for
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which OPP table is filled with the clock frequency
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and voltage corner/level.
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Example:
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clock_rpm: qcom,rpmcc@fc4000000 {
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compatible = "qcom,rpmcc-8974";
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reg = <0xfc400000 0x4000>;
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reg-names = "cc_base";
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#clock-cells = <1>;
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};
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clock_gcc: qcom,gcc@fc400000 {
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compatible = "qcom,gcc-8974";
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reg = <0xfc400000 0x4000>;
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reg-names = "cc_base";
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vdd_dig-supply = <&pm8841_s2_corner>;
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#clock-cells = <1>;
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};
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