498 lines
15 KiB
C
498 lines
15 KiB
C
/*
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* Copyright (c) 2012 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _ALX_SW_H_
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#define _ALX_SW_H_
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#include <linux/netdevice.h>
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#include <linux/crc32.h>
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/* Vendor ID */
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#define ALX_VENDOR_ID 0x1969
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/* Device IDs */
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#define ALX_DEV_ID_AR8131 0x1063 /* l1c */
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#define ALX_DEV_ID_AR8132 0x1062 /* l2c */
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#define ALX_DEV_ID_AR8151_V1 0x1073 /* l1d_v1 */
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#define ALX_DEV_ID_AR8151_V2 0x1083 /* l1d_v2 */
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#define ALX_DEV_ID_AR8152_V1 0x2060 /* l2cb_v1 */
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#define ALX_DEV_ID_AR8152_V2 0x2062 /* l2cb_v2 */
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#define ALX_DEV_ID_AR8161 0x1091 /* l1f */
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#define ALX_DEV_ID_AR8162 0x1090 /* l2f */
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#define ALX_REV_ID_AR8152_V1_0 0xc0
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#define ALX_REV_ID_AR8152_V1_1 0xc1
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#define ALX_REV_ID_AR8152_V2_0 0xc0
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#define ALX_REV_ID_AR8152_V2_1 0xc1
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#define ALX_REV_ID_AR8161_V2_0 0x10 /* B0 */
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/* Generic Registers */
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#define ALX_DEV_STAT 0x62 /* 16 bits */
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#define ALX_DEV_STAT_CERR 0x0001
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#define ALX_DEV_STAT_NFERR 0x0002
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#define ALX_DEV_STAT_FERR 0x0004
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#define ALX_ISR 0x1600
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#define ALX_IMR 0x1604
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#define ALX_ISR_SMB 0x00000001
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#define ALX_ISR_TIMER 0x00000002
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#define ALX_ISR_MANU 0x00000004
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#define ALX_ISR_RXF_OV 0x00000008
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#define ALX_ISR_RFD_UR 0x00000010
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#define ALX_ISR_TX_Q1 0x00000020
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#define ALX_ISR_TX_Q2 0x00000040
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#define ALX_ISR_TX_Q3 0x00000080
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#define ALX_ISR_TXF_UR 0x00000100
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#define ALX_ISR_DMAR 0x00000200
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#define ALX_ISR_DMAW 0x00000400
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#define ALX_ISR_TX_CREDIT 0x00000800
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#define ALX_ISR_PHY 0x00001000
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#define ALX_ISR_PHY_LPW 0x00002000
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#define ALX_ISR_TXQ_TO 0x00004000
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#define ALX_ISR_TX_Q0 0x00008000
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#define ALX_ISR_RX_Q0 0x00010000
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#define ALX_ISR_RX_Q1 0x00020000
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#define ALX_ISR_RX_Q2 0x00040000
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#define ALX_ISR_RX_Q3 0x00080000
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#define ALX_ISR_MAC_RX 0x00100000
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#define ALX_ISR_MAC_TX 0x00200000
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#define ALX_ISR_PCIE_UR 0x00400000
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#define ALX_ISR_PCIE_FERR 0x00800000
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#define ALX_ISR_PCIE_NFERR 0x01000000
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#define ALX_ISR_PCIE_CERR 0x02000000
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#define ALX_ISR_PCIE_LNKDOWN 0x04000000
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#define ALX_ISR_RX_Q4 0x08000000
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#define ALX_ISR_RX_Q5 0x10000000
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#define ALX_ISR_RX_Q6 0x20000000
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#define ALX_ISR_RX_Q7 0x40000000
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#define ALX_ISR_DIS 0x80000000
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#define ALX_IMR_NORMAL_MASK (\
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ALX_ISR_MANU |\
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ALX_ISR_OVER |\
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ALX_ISR_TXQ |\
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ALX_ISR_RXQ |\
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ALX_ISR_PHY_LPW |\
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ALX_ISR_PHY |\
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ALX_ISR_ERROR)
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#define ALX_ISR_ALERT_MASK (\
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ALX_ISR_DMAR |\
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ALX_ISR_DMAW |\
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ALX_ISR_TXQ_TO |\
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ALX_ISR_PCIE_FERR |\
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ALX_ISR_PCIE_LNKDOWN |\
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ALX_ISR_RFD_UR |\
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ALX_ISR_RXF_OV)
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#define ALX_ISR_TXQ (\
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ALX_ISR_TX_Q0 |\
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ALX_ISR_TX_Q1 |\
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ALX_ISR_TX_Q2 |\
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ALX_ISR_TX_Q3)
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#define ALX_ISR_RXQ (\
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ALX_ISR_RX_Q0 |\
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ALX_ISR_RX_Q1 |\
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ALX_ISR_RX_Q2 |\
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ALX_ISR_RX_Q3 |\
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ALX_ISR_RX_Q4 |\
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ALX_ISR_RX_Q5 |\
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ALX_ISR_RX_Q6 |\
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ALX_ISR_RX_Q7)
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#define ALX_ISR_OVER (\
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ALX_ISR_RFD_UR |\
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ALX_ISR_RXF_OV |\
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ALX_ISR_TXF_UR)
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#define ALX_ISR_ERROR (\
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ALX_ISR_DMAR |\
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ALX_ISR_TXQ_TO |\
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ALX_ISR_DMAW |\
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ALX_ISR_PCIE_ERROR)
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#define ALX_ISR_PCIE_ERROR (\
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ALX_ISR_PCIE_FERR |\
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ALX_ISR_PCIE_LNKDOWN)
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/* MISC Register */
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#define ALX_MISC 0x19C0
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#define ALX_MISC_INTNLOSC_OPEN 0x00000008
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#define ALX_CLK_GATE 0x1814
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/* DMA address */
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#define DMA_ADDR_HI_MASK 0xffffffff00000000ULL
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#define DMA_ADDR_LO_MASK 0x00000000ffffffffULL
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#define ALX_DMA_ADDR_HI(_addr) \
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((u32)(((u64)(_addr) & DMA_ADDR_HI_MASK) >> 32))
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#define ALX_DMA_ADDR_LO(_addr) \
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((u32)((u64)(_addr) & DMA_ADDR_LO_MASK))
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/* mac address length */
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#define ALX_ETH_LENGTH_OF_ADDRESS 6
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#define ALX_ETH_LENGTH_OF_HEADER ETH_HLEN
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#define ALX_ETH_CRC(_addr, _len) ether_crc((_len), (_addr));
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/* Autonegotiation advertised speeds */
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/* Link speed */
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#define ALX_LINK_SPEED_UNKNOWN 0x0
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#define ALX_LINK_SPEED_10_HALF 0x0001
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#define ALX_LINK_SPEED_10_FULL 0x0002
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#define ALX_LINK_SPEED_100_HALF 0x0004
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#define ALX_LINK_SPEED_100_FULL 0x0008
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#define ALX_LINK_SPEED_1GB_FULL 0x0020
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#define ALX_LINK_SPEED_DEFAULT (\
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ALX_LINK_SPEED_10_HALF |\
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ALX_LINK_SPEED_10_FULL |\
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ALX_LINK_SPEED_100_HALF |\
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ALX_LINK_SPEED_100_FULL |\
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ALX_LINK_SPEED_1GB_FULL)
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#define ALX_MAX_SETUP_LNK_CYCLE 100
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/* Device Type definitions for new protocol MDIO commands */
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#define ALX_MDIO_DEV_TYPE_NORM 0
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/* Wake On Lan */
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#define ALX_WOL_PHY 0x00000001 /* PHY Status Change */
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#define ALX_WOL_MAGIC 0x00000002 /* Magic Packet */
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#define ALX_MAX_EEPROM_LEN 0x200
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#define ALX_MAX_HWREG_LEN 0x200
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/* RSS Settings */
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enum alx_rss_mode {
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alx_rss_mode_disable = 0,
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alx_rss_sig_que = 1,
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alx_rss_mul_que_sig_int = 2,
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alx_rss_mul_que_mul_int = 4,
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};
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/* Flow Control Settings */
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enum alx_fc_mode {
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alx_fc_none = 0,
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alx_fc_rx_pause,
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alx_fc_tx_pause,
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alx_fc_full,
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alx_fc_default
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};
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/* WRR Restrict Settings */
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enum alx_wrr_mode {
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alx_wrr_mode_none = 0,
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alx_wrr_mode_high,
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alx_wrr_mode_high2,
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alx_wrr_mode_all
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};
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enum alx_mac_type {
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alx_mac_unknown = 0,
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alx_mac_l1c,
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alx_mac_l2c,
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alx_mac_l1d_v1,
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alx_mac_l1d_v2,
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alx_mac_l2cb_v1,
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alx_mac_l2cb_v20,
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alx_mac_l2cb_v21,
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alx_mac_l1f,
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alx_mac_l2f,
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};
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/* Statistics counters collected by the MAC */
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struct alx_hw_stats {
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/* rx */
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unsigned long rx_ok;
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unsigned long rx_bcast;
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unsigned long rx_mcast;
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unsigned long rx_pause;
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unsigned long rx_ctrl;
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unsigned long rx_fcs_err;
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unsigned long rx_len_err;
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unsigned long rx_byte_cnt;
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unsigned long rx_runt;
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unsigned long rx_frag;
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unsigned long rx_sz_64B;
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unsigned long rx_sz_127B;
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unsigned long rx_sz_255B;
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unsigned long rx_sz_511B;
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unsigned long rx_sz_1023B;
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unsigned long rx_sz_1518B;
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unsigned long rx_sz_max;
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unsigned long rx_ov_sz;
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unsigned long rx_ov_rxf;
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unsigned long rx_ov_rrd;
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unsigned long rx_align_err;
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unsigned long rx_bc_byte_cnt;
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unsigned long rx_mc_byte_cnt;
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unsigned long rx_err_addr;
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/* tx */
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unsigned long tx_ok;
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unsigned long tx_bcast;
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unsigned long tx_mcast;
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unsigned long tx_pause;
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unsigned long tx_exc_defer;
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unsigned long tx_ctrl;
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unsigned long tx_defer;
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unsigned long tx_byte_cnt;
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unsigned long tx_sz_64B;
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unsigned long tx_sz_127B;
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unsigned long tx_sz_255B;
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unsigned long tx_sz_511B;
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unsigned long tx_sz_1023B;
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unsigned long tx_sz_1518B;
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unsigned long tx_sz_max;
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unsigned long tx_single_col;
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unsigned long tx_multi_col;
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unsigned long tx_late_col;
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unsigned long tx_abort_col;
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unsigned long tx_underrun;
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unsigned long tx_trd_eop;
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unsigned long tx_len_err;
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unsigned long tx_trunc;
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unsigned long tx_bc_byte_cnt;
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unsigned long tx_mc_byte_cnt;
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unsigned long update;
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};
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/* HW callback function pointer table */
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struct alx_hw;
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struct alx_hw_callbacks {
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/* NIC */
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int (*identify_nic)(struct alx_hw *);
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/* PHY */
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int (*init_phy)(struct alx_hw *);
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int (*reset_phy)(struct alx_hw *);
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int (*read_phy_reg)(struct alx_hw *, u16, u16 *);
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int (*write_phy_reg)(struct alx_hw *, u16, u16);
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int (*apply_phy_hib_patch)(struct alx_hw *);
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/* Link */
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int (*setup_phy_link)(struct alx_hw *, u32, bool, bool);
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int (*setup_phy_link_speed)(struct alx_hw *, u32, bool, bool);
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int (*check_phy_link)(struct alx_hw *, u32 *, bool *);
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/* MAC */
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int (*reset_mac)(struct alx_hw *);
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int (*start_mac)(struct alx_hw *);
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int (*stop_mac)(struct alx_hw *);
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int (*config_mac)(struct alx_hw *, u16, u16, u16, u16, u16);
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int (*get_mac_addr)(struct alx_hw *, u8 *);
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int (*set_mac_addr)(struct alx_hw *, u8 *);
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int (*set_mc_addr)(struct alx_hw *, u8 *);
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int (*clear_mc_addr)(struct alx_hw *);
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/* intr */
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int (*ack_phy_intr)(struct alx_hw *);
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int (*enable_legacy_intr)(struct alx_hw *);
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int (*disable_legacy_intr)(struct alx_hw *);
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int (*enable_msix_intr)(struct alx_hw *, u8);
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int (*disable_msix_intr)(struct alx_hw *, u8);
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/* Configure */
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int (*config_rx)(struct alx_hw *);
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int (*config_tx)(struct alx_hw *);
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int (*config_fc)(struct alx_hw *);
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int (*config_rss)(struct alx_hw *, bool);
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int (*config_msix)(struct alx_hw *, u16, bool, bool);
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int (*config_wol)(struct alx_hw *, u32);
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int (*config_aspm)(struct alx_hw *, bool, bool);
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int (*config_mac_ctrl)(struct alx_hw *);
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int (*config_pow_save)(struct alx_hw *, u32,
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bool, bool, bool, bool);
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int (*reset_pcie)(struct alx_hw *, bool, bool);
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/* NVRam function */
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int (*check_nvram)(struct alx_hw *, bool *);
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int (*read_nvram)(struct alx_hw *, u16, u32 *);
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int (*write_nvram)(struct alx_hw *, u16, u32);
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/* Others */
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int (*get_ethtool_regs)(struct alx_hw *, void *);
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};
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struct alx_hw {
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struct alx_adapter *adpt;
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struct alx_hw_callbacks cbs;
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u8 __iomem *hw_addr; /* inner register address */
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u16 pci_venid;
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u16 pci_devid;
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u16 pci_sub_devid;
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u16 pci_sub_venid;
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u8 pci_revid;
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bool long_cable;
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bool aps_en;
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bool hi_txperf;
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bool msi_lnkpatch;
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u32 dma_chnl;
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u32 hwreg_sz;
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u32 eeprom_sz;
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/* PHY parameter */
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u32 phy_id;
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u32 autoneg_advertised;
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u32 link_speed;
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bool link_up;
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spinlock_t mdio_lock;
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bool bHibBug;
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bool bInHibMode;
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bool bHibPatched;
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/* MAC parameter */
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enum alx_mac_type mac_type;
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u8 mac_addr[ALX_ETH_LENGTH_OF_ADDRESS];
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u8 mac_perm_addr[ALX_ETH_LENGTH_OF_ADDRESS];
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u32 mtu;
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u16 rxstat_reg;
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u16 rxstat_sz;
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u16 txstat_reg;
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u16 txstat_sz;
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u16 tx_prod_reg[4];
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u16 tx_cons_reg[4];
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u16 rx_prod_reg[2];
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u16 rx_cons_reg[2];
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u64 tpdma[4];
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u64 rfdma[2];
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u64 rrdma[2];
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/* WRR parameter */
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enum alx_wrr_mode wrr_mode;
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u32 wrr_prio0;
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u32 wrr_prio1;
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u32 wrr_prio2;
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u32 wrr_prio3;
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/* RSS parameter */
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enum alx_rss_mode rss_mode;
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u8 rss_hstype;
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u8 rss_base_cpu;
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u16 rss_idt_size;
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u32 rss_idt[32];
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u8 rss_key[40];
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/* flow control parameter */
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enum alx_fc_mode cur_fc_mode; /* FC mode in effect */
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enum alx_fc_mode req_fc_mode; /* FC mode requested by caller */
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bool disable_fc_autoneg; /* Do not autonegotiate FC */
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bool fc_was_autonegged; /* the result of autonegging */
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bool fc_single_pause;
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/* Others */
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u32 preamble;
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u32 intr_mask;
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u16 smb_timer;
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u16 imt; /* Interrupt Moderator timer (2us) */
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u32 flags;
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};
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#define ALX_HW_FLAG_L0S_CAP 0x00000001
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#define ALX_HW_FLAG_L0S_EN 0x00000002
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#define ALX_HW_FLAG_L1_CAP 0x00000004
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#define ALX_HW_FLAG_L1_EN 0x00000008
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#define ALX_HW_FLAG_PWSAVE_CAP 0x00000010
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#define ALX_HW_FLAG_PWSAVE_EN 0x00000020
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#define ALX_HW_FLAG_AZ_CAP 0x00000040
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#define ALX_HW_FLAG_AZ_EN 0x00000080
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#define ALX_HW_FLAG_PTP_CAP 0x00000100
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#define ALX_HW_FLAG_PTP_EN 0x00000200
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#define ALX_HW_FLAG_GIGA_CAP 0x00000400
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#define ALX_HW_FLAG_PROMISC_EN 0x00010000 /* for mac ctrl reg */
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#define ALX_HW_FLAG_VLANSTRIP_EN 0x00020000 /* for mac ctrl reg */
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#define ALX_HW_FLAG_MULTIALL_EN 0x00040000 /* for mac ctrl reg */
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#define ALX_HW_FLAG_LOOPBACK_EN 0x00080000 /* for mac ctrl reg */
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#define CHK_HW_FLAG(_flag) CHK_FLAG(hw, HW, _flag)
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#define SET_HW_FLAG(_flag) SET_FLAG(hw, HW, _flag)
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#define CLI_HW_FLAG(_flag) CLI_FLAG(hw, HW, _flag)
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/* RSS hstype Definitions */
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#define ALX_RSS_HSTYP_IPV4_EN 0x00000001
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#define ALX_RSS_HSTYP_TCP4_EN 0x00000002
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#define ALX_RSS_HSTYP_IPV6_EN 0x00000004
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#define ALX_RSS_HSTYP_TCP6_EN 0x00000008
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#define ALX_RSS_HSTYP_ALL_EN (\
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ALX_RSS_HSTYP_IPV4_EN |\
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ALX_RSS_HSTYP_TCP4_EN |\
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ALX_RSS_HSTYP_IPV6_EN |\
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ALX_RSS_HSTYP_TCP6_EN)
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/* definitions for flags */
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#define CHK_FLAG_ARRAY(_st, _idx, _type, _flag) \
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((_st)->flags[_idx] & (ALX_##_type##_FLAG_##_idx##_##_flag))
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#define CHK_FLAG(_st, _type, _flag) \
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((_st)->flags & (ALX_##_type##_FLAG_##_flag))
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#define SET_FLAG_ARRAY(_st, _idx, _type, _flag) \
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((_st)->flags[_idx] |= (ALX_##_type##_FLAG_##_idx##_##_flag))
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#define SET_FLAG(_st, _type, _flag) \
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((_st)->flags |= (ALX_##_type##_FLAG_##_flag))
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#define CLI_FLAG_ARRAY(_st, _idx, _type, _flag) \
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((_st)->flags[_idx] &= ~(ALX_##_type##_FLAG_##_idx##_##_flag))
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#define CLI_FLAG(_st, _type, _flag) \
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((_st)->flags &= ~(ALX_##_type##_FLAG_##_flag))
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int alx_cfg_r16(const struct alx_hw *hw, int reg, u16 *pval);
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int alx_cfg_w16(const struct alx_hw *hw, int reg, u16 val);
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void alx_mem_flush(const struct alx_hw *hw);
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void alx_mem_r32(const struct alx_hw *hw, int reg, u32 *val);
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void alx_mem_w32(const struct alx_hw *hw, int reg, u32 val);
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void alx_mem_w8(const struct alx_hw *hw, int reg, u8 val);
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/* special definitions for hw */
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#define ALF_MAX_MSIX_NOQUE_INTRS 4
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#define ALF_MIN_MSIX_NOQUE_INTRS 4
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#define ALF_MAX_MSIX_QUEUE_INTRS 12
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#define ALF_MIN_MSIX_QUEUE_INTRS 12
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#define ALF_MAX_MSIX_INTRS \
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(ALF_MAX_MSIX_QUEUE_INTRS + ALF_MAX_MSIX_NOQUE_INTRS)
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#define ALF_MIN_MSIX_INTRS \
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(ALF_MIN_MSIX_NOQUE_INTRS + ALF_MIN_MSIX_QUEUE_INTRS)
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/* function */
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extern int alc_init_hw_callbacks(struct alx_hw *hw);
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extern int alf_init_hw_callbacks(struct alx_hw *hw);
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/* Logging message functions */
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void __printf(3, 4) alx_hw_printk(const char *level, const struct alx_hw *hw,
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const char *fmt, ...);
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#define alx_hw_err(_hw, _format, ...) \
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alx_hw_printk(KERN_ERR, _hw, _format, ##__VA_ARGS__)
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#define alx_hw_warn(_hw, _format, ...) \
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alx_hw_printk(KERN_WARNING, _hw, _format, ##__VA_ARGS__)
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#define alx_hw_info(_hw, _format, ...) \
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alx_hw_printk(KERN_INFO, _hw, _format, ##__VA_ARGS__)
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#endif /* _ALX_SW_H_ */
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