381 lines
9.9 KiB
C
Executable File
381 lines
9.9 KiB
C
Executable File
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <smem.h>
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#include <err.h>
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#include <msm_panel.h>
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#include <mipi_dsi.h>
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#include <pm8x41.h>
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#include <pm8x41_wled.h>
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#include <board.h>
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#include <mdp3.h>
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#include <scm.h>
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#include <platform/gpio.h>
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#include <platform/iomap.h>
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#include <target/display.h>
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#include <regulator.h>
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#include "include/panel.h"
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#include "include/display_resource.h"
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#include "gcdb_display.h"
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#define VCO_DELAY_USEC 1000
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#define GPIO_STATE_LOW 0
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#define GPIO_STATE_HIGH 2
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#define RESET_GPIO_SEQ_LEN 3
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#define PWM_DUTY_US 13
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#define PWM_PERIOD_US 27
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#define PM8916_VER 0x20000
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static void mdss_dsi_uniphy_pll_sw_reset_8909(uint32_t pll_base)
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{
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writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */
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mdelay(1);
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writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */
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mdelay(1);
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}
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static void dsi_pll_toggle_lock_detect_8909(uint32_t pll_base)
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{
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writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */
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udelay(1);
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writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */
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udelay(512);
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}
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static void dsi_pll_sw_reset_8909(uint32_t pll_base)
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{
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writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */
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udelay(1);
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writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */
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}
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static uint32_t dsi_pll_enable_seq_1_8909(uint32_t pll_base)
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{
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uint32_t rc;
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dsi_pll_sw_reset_8909(pll_base);
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/*
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* Add hardware recommended delays between register writes for
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* the updates to take effect. These delays are necessary for the
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* PLL to successfully lock
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*/
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writel(0x34, pll_base + 0x0070); /* CAL CFG1*/
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writel(0x01, pll_base + 0x0020); /* GLB CFG */
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writel(0x05, pll_base + 0x0020); /* GLB CFG */
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writel(0x0f, pll_base + 0x0020); /* GLB CFG */
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udelay(500);
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dsi_pll_toggle_lock_detect_8909(pll_base);
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rc = readl(pll_base + 0x00c0) & 0x01;
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return rc;
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}
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static uint32_t dsi_pll_enable_seq_2_8909(uint32_t pll_base)
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{
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uint32_t rc;
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dsi_pll_sw_reset_8909(pll_base);
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/*
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* Add hardware recommended delays between register writes for
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* the updates to take effect. These delays are necessary for the
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* PLL to successfully lock
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*/
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writel(0x14, pll_base + 0x0070); /* CAL CFG1*/
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writel(0x01, pll_base + 0x0020); /* GLB CFG */
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writel(0x05, pll_base + 0x0020); /* GLB CFG */
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udelay(3);
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writel(0x0f, pll_base + 0x0020); /* GLB CFG */
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udelay(500);
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dsi_pll_toggle_lock_detect_8909(pll_base);
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rc = readl(pll_base + 0x00c0) & 0x01;
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return rc;
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}
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static uint32_t dsi_pll_enable_seq_3_8909(uint32_t pll_base)
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{
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uint32_t rc;
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dsi_pll_sw_reset_8909(pll_base);
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/*
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* Add hardware recommended delays between register writes for
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* the updates to take effect. These delays are necessary for the
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* PLL to successfully lock
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*/
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writel(0x04, pll_base + 0x0070); /* CAL CFG1*/
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writel(0x01, pll_base + 0x0020); /* GLB CFG */
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writel(0x05, pll_base + 0x0020); /* GLB CFG */
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udelay(3);
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writel(0x0f, pll_base + 0x0020); /* GLB CFG */
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udelay(500);
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dsi_pll_toggle_lock_detect_8909(pll_base);
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rc = readl(pll_base + 0x00c0) & 0x01;
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return rc;
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}
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static uint32_t dsi_pll_enable_seq_8909(uint32_t pll_base)
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{
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uint32_t pll_locked = 0;
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uint32_t counter = 0;
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do {
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pll_locked = dsi_pll_enable_seq_1_8909(pll_base);
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dprintf(SPEW, "TSMC pll locked status is %d\n", pll_locked);
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++counter;
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} while (!pll_locked && (counter < 3));
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if (!pll_locked) {
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counter = 0;
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do {
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pll_locked = dsi_pll_enable_seq_2_8909(pll_base);
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dprintf(SPEW, "GF P1 pll locked status is %d\n",
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pll_locked);
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++counter;
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} while (!pll_locked && (counter < 3));
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}
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if (!pll_locked) {
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counter = 0;
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do {
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pll_locked = dsi_pll_enable_seq_3_8909(pll_base);
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dprintf(SPEW, "GF P2 pll locked status is %d\n",
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pll_locked);
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++counter;
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} while (!pll_locked && (counter < 3));
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}
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return pll_locked;
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}
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int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
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{
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struct pm8x41_mpp mpp;
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uint32_t hw_id = board_hardware_id();
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struct board_pmic_data pmic_info;
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int rc;
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if (bl->bl_interface_type == BL_DCS)
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return 0;
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board_pmic_info(&pmic_info, 1);
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if (pmic_info.pmic_version == PM8916_VER)
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mpp.base = PM8x41_MMP4_BASE;
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else
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mpp.base = PM8x41_MMP2_BASE;
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mpp.vin = MPP_VIN0;
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if (enable) {
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pm_pwm_enable(false);
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rc = pm_pwm_config(PWM_DUTY_US, PWM_PERIOD_US);
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if (rc < 0)
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mpp.mode = MPP_HIGH;
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else {
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mpp.mode = MPP_DTEST1;
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pm_pwm_enable(true);
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}
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pm8x41_config_output_mpp(&mpp);
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pm8x41_enable_mpp(&mpp, MPP_ENABLE);
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} else {
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pm_pwm_enable(false);
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pm8x41_enable_mpp(&mpp, MPP_DISABLE);
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}
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mdelay(20);
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if (enable) {
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gpio_tlmm_config(bkl_gpio.pin_id, 0,
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bkl_gpio.pin_direction, bkl_gpio.pin_pull,
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bkl_gpio.pin_strength, bkl_gpio.pin_state);
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gpio_set(bkl_gpio.pin_id, 2);
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}
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return 0;
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}
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int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
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{
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int32_t ret = 0;
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struct mdss_dsi_pll_config *pll_data;
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dprintf(SPEW, "target_panel_clock\n");
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pll_data = pinfo->mipi.dsi_pll_config;
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pll_data->vco_delay = VCO_DELAY_USEC;
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if (enable) {
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mdp_gdsc_ctrl(enable);
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mdss_bus_clocks_enable();
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mdp_clock_enable();
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/*
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* Enable auto functional gating
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* on DSI CMD AXI fetch from DDR
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*/
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writel(0x3fbff, MDP_CGC_EN);
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ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
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if (ret) {
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dprintf(CRITICAL,
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"%s: Failed to restore MDP security configs",
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__func__);
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mdp_clock_disable();
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mdss_bus_clocks_disable();
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mdp_gdsc_ctrl(0);
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return ret;
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}
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mdss_dsi_uniphy_pll_sw_reset_8909(pinfo->mipi.pll_base);
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mdss_dsi_auto_pll_config(pinfo->mipi.pll_base,
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pinfo->mipi.ctl_base, pll_data);
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if (!dsi_pll_enable_seq_8909(pinfo->mipi.pll_base))
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dprintf(CRITICAL, "Not able to enable the pll\n");
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gcc_dsi_clocks_enable(pll_data->pclk_m,
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pll_data->pclk_n,
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pll_data->pclk_d);
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} else if(!target_cont_splash_screen()) {
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gcc_dsi_clocks_disable();
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mdp_clock_disable();
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mdss_bus_clocks_disable();
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mdp_gdsc_ctrl(enable);
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}
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return 0;
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}
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int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
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struct msm_panel_info *pinfo)
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{
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int ret = NO_ERROR;
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uint32_t hw_id = board_hardware_id();
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uint32_t hw_subtype = board_hardware_subtype();
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if (enable) {
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if (pinfo->mipi.use_enable_gpio) {
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gpio_tlmm_config(enable_gpio.pin_id, 0,
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enable_gpio.pin_direction, enable_gpio.pin_pull,
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enable_gpio.pin_strength,
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enable_gpio.pin_state);
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gpio_set(enable_gpio.pin_id, 2);
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}
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gpio_tlmm_config(reset_gpio.pin_id, 0,
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reset_gpio.pin_direction, reset_gpio.pin_pull,
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reset_gpio.pin_strength, reset_gpio.pin_state);
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gpio_set(reset_gpio.pin_id, 2);
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/* reset */
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for (int i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
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if (resetseq->pin_state[i] == GPIO_STATE_LOW)
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gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW);
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else
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gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH);
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mdelay(resetseq->sleep[i]);
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}
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} else if(!target_cont_splash_screen()) {
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gpio_set(reset_gpio.pin_id, 0);
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if (pinfo->mipi.use_enable_gpio)
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gpio_set(enable_gpio.pin_id, 0);
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}
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return ret;
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}
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int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
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{
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if (enable)
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regulator_enable(REG_LDO2 | REG_LDO6 | REG_LDO17);
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return NO_ERROR;
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}
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int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db)
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{
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memcpy(phy_db->regulator, panel_regulator_settings, REGULATOR_SIZE);
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memcpy(phy_db->ctrl, panel_physical_ctrl, PHYSICAL_SIZE);
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memcpy(phy_db->strength, panel_strength_ctrl, STRENGTH_SIZE);
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memcpy(phy_db->bistCtrl, panel_bist_ctrl, BIST_SIZE);
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memcpy(phy_db->laneCfg, panel_lane_config, LANE_SIZE);
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return NO_ERROR;
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}
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bool target_display_panel_node(char *pbuf, uint16_t buf_size)
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{
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return gcdb_display_cmdline_arg(pbuf, buf_size);
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}
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void target_display_init(const char *panel_name)
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{
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uint32_t panel_loop = 0;
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uint32_t ret = 0;
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struct oem_panel_data oem;
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set_panel_cmd_string(panel_name);
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oem = mdss_dsi_get_oem_data();
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if (!strcmp(oem.panel, NO_PANEL_CONFIG)
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|| !strcmp(oem.panel, SIM_VIDEO_PANEL)
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|| !strcmp(oem.panel, SIM_CMD_PANEL)
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|| oem.skip) {
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dprintf(INFO, "Selected %s: Skip panel configuration\n",
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oem.panel);
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return;
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}
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do {
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target_force_cont_splash_disable(false);
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ret = gcdb_display_init(oem.panel, MDP_REV_305, MIPI_FB_ADDR);
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if (!ret || ret == ERR_NOT_SUPPORTED) {
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break;
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} else {
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target_force_cont_splash_disable(true);
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msm_display_off();
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}
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} while (++panel_loop <= oem_panel_max_auto_detect_panels());
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if (!oem.cont_splash) {
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dprintf(INFO, "Forcing continuous splash disable\n");
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target_force_cont_splash_disable(true);
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}
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}
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void target_display_shutdown(void)
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{
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gcdb_display_shutdown();
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}
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