555 lines
15 KiB
C
Executable File
555 lines
15 KiB
C
Executable File
/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <smem.h>
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#include <err.h>
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#include <msm_panel.h>
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#include <mipi_dsi.h>
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#include <pm8x41.h>
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#include <pm8x41_wled.h>
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#include <board.h>
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#include <mdp5.h>
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#include <scm.h>
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#include <endian.h>
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#include <platform/gpio.h>
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#include <platform/clock.h>
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#include <platform/iomap.h>
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#include <target/display.h>
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#include "include/panel.h"
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#include "include/display_resource.h"
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#include "gcdb_display.h"
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#define HFPLL_LDO_ID 12
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#define GPIO_STATE_LOW 0
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#define GPIO_STATE_HIGH 2
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#define RESET_GPIO_SEQ_LEN 3
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static struct backlight edp_bklt = {
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0, 1, 4095, 100, 1, "PMIC_8941"
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};
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static uint32_t dsi_pll_lock_status(uint32_t pll_base)
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{
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uint32_t counter, status;
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udelay(100);
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mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
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status = readl(pll_base + 0x00c0) & 0x01;
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for (counter = 0; counter < 5 && !status; counter++) {
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udelay(100);
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status = readl(pll_base + 0x00c0) & 0x01;
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}
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return status;
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}
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static uint32_t dsi_pll_enable_seq_b(uint32_t pll_base)
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{
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mdss_dsi_uniphy_pll_sw_reset(pll_base);
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writel(0x01, pll_base + 0x0020); /* GLB CFG */
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udelay(1);
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writel(0x05, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x07, pll_base + 0x0020); /* GLB CFG */
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udelay(500);
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writel(0x0f, pll_base + 0x0020); /* GLB CFG */
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udelay(500);
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return dsi_pll_lock_status(pll_base);
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}
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static uint32_t dsi_pll_enable_seq_d(uint32_t pll_base)
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{
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mdss_dsi_uniphy_pll_sw_reset(pll_base);
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writel(0x01, pll_base + 0x0020); /* GLB CFG */
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udelay(1);
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writel(0x05, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x07, pll_base + 0x0020); /* GLB CFG */
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udelay(250);
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writel(0x05, pll_base + 0x0020); /* GLB CFG */
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udelay(200);
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writel(0x07, pll_base + 0x0020); /* GLB CFG */
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udelay(500);
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writel(0x0f, pll_base + 0x0020); /* GLB CFG */
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udelay(500);
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return dsi_pll_lock_status(pll_base);
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}
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static void dsi_pll_enable_seq(uint32_t pll_base)
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{
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uint32_t counter, status;
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for (counter = 0; counter < 3; counter++) {
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status = dsi_pll_enable_seq_b(pll_base);
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if (status)
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break;
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status = dsi_pll_enable_seq_d(pll_base);
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if (status)
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break;
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status = dsi_pll_enable_seq_d(pll_base);
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if(status)
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break;
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}
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if (!status)
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dprintf(CRITICAL, "Pll lock sequence failed\n");
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}
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int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
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{
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struct pm8x41_gpio pwmgpio_param = {
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.direction = PM_GPIO_DIR_OUT,
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.function = PM_GPIO_FUNC_1,
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.vin_sel = 2, /* VIN_2 */
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.pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
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.output_buffer = PM_GPIO_OUT_CMOS,
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.out_strength = 0x03,
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};
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if (enable) {
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pm8x41_gpio_config(pwm_gpio.pin_id, &pwmgpio_param);
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/* lpg channel 3 */
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pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
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pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
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pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
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pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x44, 0xcc); /* LPG_VALUE_LSB */
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pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x45, 0x00); /* LPG_VALUE_MSB */
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pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
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} else {
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pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0x0); /* LPG_ENABLE_CONTROL */
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}
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return NO_ERROR;
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}
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int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
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{
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uint32_t ret;
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struct mdss_dsi_pll_config *pll_data;
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uint32_t dual_dsi = pinfo->mipi.dual_dsi;
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dprintf(SPEW, "target_panel_clock\n");
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pll_data = pinfo->mipi.dsi_pll_config;
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if (enable) {
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mdp_gdsc_ctrl(enable);
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mmss_bus_clock_enable();
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mdp_clock_enable();
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ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
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if (ret) {
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dprintf(CRITICAL,
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"%s: Failed to restore MDP security configs",
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__func__);
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mdp_clock_disable();
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mmss_bus_clock_disable();
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mdp_gdsc_ctrl(0);
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return ret;
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}
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mdss_dsi_auto_pll_config(pinfo->mipi.pll_base,
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pinfo->mipi.ctl_base, pll_data);
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dsi_pll_enable_seq(pinfo->mipi.pll_base);
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mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
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pll_data->pclk_m,
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pll_data->pclk_n,
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pll_data->pclk_d);
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} else if(!target_cont_splash_screen()) {
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/* Disable clocks if continuous splash off */
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mmss_dsi_clock_disable(dual_dsi);
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mdp_clock_disable();
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mmss_bus_clock_disable();
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mdp_gdsc_ctrl(enable);
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}
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return NO_ERROR;
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}
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/* Pull DISP_RST_N high to get panel out of reset */
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int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
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struct msm_panel_info *pinfo)
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{
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uint32_t i = 0;
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if (enable) {
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gpio_tlmm_config(reset_gpio.pin_id, 0,
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reset_gpio.pin_direction, reset_gpio.pin_pull,
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reset_gpio.pin_strength, reset_gpio.pin_state);
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gpio_tlmm_config(enable_gpio.pin_id, 0,
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enable_gpio.pin_direction, enable_gpio.pin_pull,
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enable_gpio.pin_strength, enable_gpio.pin_state);
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gpio_tlmm_config(bkl_gpio.pin_id, 0,
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bkl_gpio.pin_direction, bkl_gpio.pin_pull,
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bkl_gpio.pin_strength, bkl_gpio.pin_state);
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gpio_set(enable_gpio.pin_id, 2);
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gpio_set(bkl_gpio.pin_id, 2);
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/* reset */
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for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
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if (resetseq->pin_state[i] == GPIO_STATE_LOW)
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gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW);
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else
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gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH);
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mdelay(resetseq->sleep[i]);
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}
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} else {
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gpio_set(reset_gpio.pin_id, 0);
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gpio_set(enable_gpio.pin_id, 0);
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gpio_set(bkl_gpio.pin_id, 0);
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}
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return NO_ERROR;
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}
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int target_ldo_ctrl(uint8_t enable, struct msm_panel_info *pinfo)
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{
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uint32_t ldocounter = 0;
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uint32_t pm8x41_ldo_base = 0x13F00;
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while (ldocounter < TOTAL_LDO_DEFINED) {
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struct pm8x41_ldo ldo_entry = LDO((pm8x41_ldo_base +
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0x100 * ldo_entry_array[ldocounter].ldo_id),
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ldo_entry_array[ldocounter].ldo_type);
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dprintf(SPEW, "Setting %s\n",
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ldo_entry_array[ldocounter].ldo_id);
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/* Set voltage during power on */
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if (enable) {
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pm8x41_ldo_set_voltage(&ldo_entry,
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ldo_entry_array[ldocounter].ldo_voltage);
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pm8x41_ldo_control(&ldo_entry, enable);
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} else if(ldo_entry_array[ldocounter].ldo_id != HFPLL_LDO_ID) {
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pm8x41_ldo_control(&ldo_entry, enable);
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}
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ldocounter++;
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}
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return NO_ERROR;
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}
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int target_dsi_phy_config(struct mdss_dsi_phy_ctrl *phy_db)
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{
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memcpy(phy_db->regulator, panel_regulator_settings, REGULATOR_SIZE);
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memcpy(phy_db->ctrl, panel_physical_ctrl, PHYSICAL_SIZE);
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memcpy(phy_db->strength, panel_strength_ctrl, STRENGTH_SIZE);
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memcpy(phy_db->bistCtrl, panel_bist_ctrl, BIST_SIZE);
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memcpy(phy_db->laneCfg, panel_lane_config, LANE_SIZE);
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return NO_ERROR;
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}
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int target_display_pre_on()
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{
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writel(0x000000FA, MDP_QOS_REMAPPER_CLASS_0);
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writel(0x00000055, MDP_QOS_REMAPPER_CLASS_1);
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writel(0xC0000CCD, MDP_CLK_CTRL0);
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writel(0xD0000CCC, MDP_CLK_CTRL1);
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writel(0x00CCCCCC, MDP_CLK_CTRL2);
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writel(0x000000CC, MDP_CLK_CTRL6);
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writel(0x0CCCC0C0, MDP_CLK_CTRL3);
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writel(0xCCCCC0C0, MDP_CLK_CTRL4);
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writel(0xCCCCC0C0, MDP_CLK_CTRL5);
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writel(0x00CCC000, MDP_CLK_CTRL7);
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writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF0);
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writel(0x08000808, VBIF_VBIF_IN_RD_LIM_CONF1);
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writel(0x00080808, VBIF_VBIF_IN_RD_LIM_CONF2);
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writel(0x00000808, VBIF_VBIF_IN_RD_LIM_CONF3);
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writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF0);
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writel(0x00100000, VBIF_VBIF_IN_WR_LIM_CONF1);
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writel(0x10000000, VBIF_VBIF_IN_WR_LIM_CONF2);
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writel(0x00000000, VBIF_VBIF_IN_WR_LIM_CONF3);
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writel(0x00013fff, VBIF_VBIF_ABIT_SHORT);
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writel(0x000000A4, VBIF_VBIF_ABIT_SHORT_CONF);
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writel(0x00003FFF, VBIF_VBIF_GATE_OFF_WRREQ_EN);
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writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB);
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return NO_ERROR;
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}
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int target_hdmi_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
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{
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uint32_t ret;
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dprintf(SPEW, "%s: target_panel_clock\n", __func__);
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if (enable) {
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mdp_gdsc_ctrl(enable);
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mmss_bus_clock_enable();
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mdp_clock_enable();
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ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
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if (ret) {
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dprintf(CRITICAL,
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"%s: Failed to restore MDP security configs",
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__func__);
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mdp_clock_disable();
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mmss_bus_clock_disable();
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mdp_gdsc_ctrl(0);
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return ret;
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}
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hdmi_phy_reset();
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hdmi_pll_config();
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hdmi_vco_enable();
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hdmi_clk_enable();
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} else if(!target_cont_splash_screen()) {
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/* Disable clocks if continuous splash off */
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hdmi_clk_disable();
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hdmi_vco_disable();
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mdp_clock_disable();
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mmss_bus_clock_disable();
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mdp_gdsc_ctrl(enable);
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}
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return NO_ERROR;
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}
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static void target_hdmi_mvs_enable(bool enable)
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{
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struct pm8x41_mvs mvs;
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mvs.base = PM8x41_MVS1_BASE;
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if (enable)
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pm8x41_enable_mvs(&mvs, MVS_ENABLE);
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else
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pm8x41_enable_mvs(&mvs, MVS_DISABLE);
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}
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static void target_hdmi_vreg_enable(bool enable)
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{
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struct pm8x41_mpp mpp;
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mpp.base = PM8x41_MMP3_BASE;
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if (enable) {
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mpp.mode = MPP_HIGH;
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mpp.vin = MPP_VIN2;
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pm8x41_config_output_mpp(&mpp);
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pm8x41_enable_mpp(&mpp, MPP_ENABLE);
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} else {
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pm8x41_enable_mpp(&mpp, MPP_DISABLE);
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}
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}
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int target_hdmi_regulator_ctrl(bool enable)
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{
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target_hdmi_mvs_enable(enable);
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target_hdmi_vreg_enable(enable);
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return 0;
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}
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int target_hdmi_gpio_ctrl(bool enable)
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{
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gpio_tlmm_config(hdmi_cec_gpio.pin_id, 1, /* gpio 31, CEC */
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hdmi_cec_gpio.pin_direction, hdmi_cec_gpio.pin_pull,
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hdmi_cec_gpio.pin_strength, hdmi_cec_gpio.pin_state);
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gpio_tlmm_config(hdmi_ddc_clk_gpio.pin_id, 1, /* gpio 32, DDC CLK */
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hdmi_ddc_clk_gpio.pin_direction, hdmi_ddc_clk_gpio.pin_pull,
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hdmi_ddc_clk_gpio.pin_strength, hdmi_ddc_clk_gpio.pin_state);
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gpio_tlmm_config(hdmi_ddc_data_gpio.pin_id, 1, /* gpio 33, DDC DATA */
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hdmi_ddc_data_gpio.pin_direction, hdmi_ddc_data_gpio.pin_pull,
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hdmi_ddc_data_gpio.pin_strength, hdmi_ddc_data_gpio.pin_state);
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gpio_tlmm_config(hdmi_hpd_gpio.pin_id, 1, /* gpio 34, HPD */
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hdmi_hpd_gpio.pin_direction, hdmi_hpd_gpio.pin_pull,
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hdmi_hpd_gpio.pin_strength, hdmi_hpd_gpio.pin_state);
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gpio_set(hdmi_cec_gpio.pin_id, hdmi_cec_gpio.pin_direction);
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gpio_set(hdmi_ddc_clk_gpio.pin_id, hdmi_ddc_clk_gpio.pin_direction);
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gpio_set(hdmi_ddc_data_gpio.pin_id, hdmi_ddc_data_gpio.pin_direction);
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gpio_set(hdmi_hpd_gpio.pin_id, hdmi_hpd_gpio.pin_direction);
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/* MUX */
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gpio_tlmm_config(hdmi_mux_lpm_gpio.pin_id, 0, /* gpio 27 MUX LPM */
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hdmi_mux_lpm_gpio.pin_direction, hdmi_mux_lpm_gpio.pin_pull,
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hdmi_mux_lpm_gpio.pin_strength, hdmi_mux_lpm_gpio.pin_state);
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gpio_tlmm_config(hdmi_mux_en_gpio.pin_id, 0, /* gpio 83 MUX EN */
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hdmi_mux_en_gpio.pin_direction, hdmi_mux_en_gpio.pin_pull,
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hdmi_mux_en_gpio.pin_strength, hdmi_mux_en_gpio.pin_state);
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gpio_tlmm_config(hdmi_mux_sel_gpio.pin_id, 0, /* gpio 85 MUX SEL */
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hdmi_mux_sel_gpio.pin_direction, hdmi_mux_sel_gpio.pin_pull,
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hdmi_mux_sel_gpio.pin_strength, hdmi_mux_sel_gpio.pin_state);
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gpio_set(hdmi_mux_lpm_gpio.pin_id, hdmi_mux_lpm_gpio.pin_direction);
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gpio_set(hdmi_mux_en_gpio.pin_id, hdmi_mux_en_gpio.pin_direction);
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gpio_set(hdmi_mux_sel_gpio.pin_id, hdmi_mux_sel_gpio.pin_direction);
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return NO_ERROR;
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}
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void target_edp_panel_init(struct msm_panel_info *pinfo)
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{
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edp_panel_init(pinfo);
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}
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int target_edp_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
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{
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uint32_t ret;
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dprintf(SPEW, "%s: target_panel_clock\n", __func__);
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if (enable) {
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mdp_gdsc_ctrl(enable);
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mmss_bus_clock_enable();
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mdp_clock_enable();
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ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
|
|
if (ret) {
|
|
dprintf(CRITICAL,
|
|
"%s: Failed to restore MDP security configs",
|
|
__func__);
|
|
mdp_clock_disable();
|
|
mmss_bus_clock_disable();
|
|
mdp_gdsc_ctrl(0);
|
|
return ret;
|
|
}
|
|
|
|
edp_clk_enable();
|
|
} else if(!target_cont_splash_screen()) {
|
|
/* Disable clocks if continuous splash off */
|
|
edp_clk_disable();
|
|
mdp_clock_disable();
|
|
mmss_bus_clock_disable();
|
|
mdp_gdsc_ctrl(enable);
|
|
}
|
|
|
|
return NO_ERROR;
|
|
}
|
|
|
|
int target_edp_panel_enable(void)
|
|
{
|
|
gpio_tlmm_config(enable_gpio.pin_id, 0, /* gpio 137 */
|
|
enable_gpio.pin_direction, enable_gpio.pin_pull,
|
|
enable_gpio.pin_strength, enable_gpio.pin_state);
|
|
|
|
|
|
gpio_tlmm_config(edp_hpd_gpio.pin_id, 0, /* hpd 103 */
|
|
edp_hpd_gpio.pin_direction, edp_hpd_gpio.pin_pull,
|
|
edp_hpd_gpio.pin_strength, edp_hpd_gpio.pin_state);
|
|
|
|
|
|
gpio_tlmm_config(edp_lvl_en_gpio.pin_id, 0, /* lvl_en 91 */
|
|
edp_lvl_en_gpio.pin_direction, edp_lvl_en_gpio.pin_pull,
|
|
edp_lvl_en_gpio.pin_strength, edp_lvl_en_gpio.pin_state);
|
|
|
|
gpio_set(enable_gpio.pin_id, 2);
|
|
gpio_set(edp_lvl_en_gpio.pin_id, 2);
|
|
|
|
return NO_ERROR;
|
|
}
|
|
|
|
int target_edp_panel_disable(void)
|
|
{
|
|
gpio_set(edp_lvl_en_gpio.pin_id, 0);
|
|
gpio_set(enable_gpio.pin_id, 0);
|
|
|
|
return NO_ERROR;
|
|
}
|
|
|
|
int target_edp_bl_ctrl(int enable)
|
|
{
|
|
return target_backlight_ctrl(&edp_bklt, enable);
|
|
}
|
|
|
|
bool target_display_panel_node(char *pbuf, uint16_t buf_size)
|
|
{
|
|
int prefix_string_len = strlen(DISPLAY_CMDLINE_PREFIX);
|
|
bool ret = true;
|
|
struct oem_panel_data oem = mdss_dsi_get_oem_data();
|
|
|
|
if (!strcmp(oem.panel, HDMI_PANEL_NAME)) {
|
|
if (buf_size < (prefix_string_len + LK_OVERRIDE_PANEL_LEN +
|
|
strlen(HDMI_CONTROLLER_STRING))) {
|
|
dprintf(CRITICAL, "command line argument is greater than buffer size\n");
|
|
return false;
|
|
}
|
|
|
|
strlcpy(pbuf, DISPLAY_CMDLINE_PREFIX, buf_size);
|
|
buf_size -= prefix_string_len;
|
|
strlcat(pbuf, LK_OVERRIDE_PANEL, buf_size);
|
|
buf_size -= LK_OVERRIDE_PANEL_LEN;
|
|
strlcat(pbuf, HDMI_CONTROLLER_STRING, buf_size);
|
|
} else {
|
|
ret = gcdb_display_cmdline_arg(pbuf, buf_size);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
void target_display_init(const char *panel_name)
|
|
{
|
|
uint32_t ret = 0;
|
|
struct oem_panel_data oem;
|
|
|
|
set_panel_cmd_string(panel_name);
|
|
oem = mdss_dsi_get_oem_data();
|
|
|
|
if (!strcmp(oem.panel, NO_PANEL_CONFIG)
|
|
|| !strcmp(oem.panel, SIM_VIDEO_PANEL)
|
|
|| !strcmp(oem.panel, SIM_DUALDSI_VIDEO_PANEL)
|
|
|| !strcmp(oem.panel, SIM_CMD_PANEL)
|
|
|| !strcmp(oem.panel, SIM_DUALDSI_CMD_PANEL)
|
|
|| oem.skip) {
|
|
dprintf(INFO, "Selected panel: %s\nSkip panel configuration\n",
|
|
oem.panel);
|
|
return;
|
|
} else if (!strcmp(oem.panel, HDMI_PANEL_NAME)) {
|
|
dprintf(INFO, "%s: HDMI is primary\n", __func__);
|
|
mdss_hdmi_display_init(MDP_REV_50, HDMI_FB_ADDR);
|
|
return;
|
|
}
|
|
|
|
ret = gcdb_display_init(oem.panel, MDP_REV_50, MIPI_FB_ADDR);
|
|
if (ret) {
|
|
target_force_cont_splash_disable(true);
|
|
msm_display_off();
|
|
}
|
|
|
|
if (!oem.cont_splash) {
|
|
dprintf(INFO, "Forcing continuous splash disable\n");
|
|
target_force_cont_splash_disable(true);
|
|
}
|
|
}
|
|
|
|
void target_display_shutdown(void)
|
|
{
|
|
gcdb_display_shutdown();
|
|
}
|