267 lines
7.9 KiB
C
267 lines
7.9 KiB
C
/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* The USB 3.0 core wrapper in MSM chipset includes:
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* - DWC core
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* - PHY control and configuration
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* - Configuration and buffers to be provided to the DWC core.
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*
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* This file implements the USB30 core wrapper configuration functions.
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* Core wrapper glues the dwc usb controller into msm chip.
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*/
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#include <debug.h>
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#include <reg.h>
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#include <malloc.h>
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#include <assert.h>
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#include <board.h>
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#include <pm8x41.h>
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#include <platform/iomap.h>
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#include <platform/timer.h>
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#include <platform/iomap.h>
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#include <platform/clock.h>
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#include <usb30_wrapper.h>
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#include <usb30_wrapper_hwio.h>
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#include <qmp_phy.h>
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/* Configure DBM mode: by-pass or DBM */
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void usb_wrapper_dbm_mode(usb_wrapper_dev_t *dev, dbm_mode_t mode)
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{
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if (mode == DBM_MODE_BYPASS)
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{
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REG_WRITE_FIELD(dev, GENERAL_CFG, DBM_EN, 0);
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}
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else
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{
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REG_WRITE_FIELD(dev, GENERAL_CFG, DBM_EN, 1);
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}
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}
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/* use config 0: all of RAM1 */
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void usb_wrapper_ram_configure(usb_wrapper_dev_t *dev)
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{
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REG_WRITE(dev, RAM1_REG, 0x0);
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}
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/* reset SS phy */
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void usb_wrapper_ss_phy_reset(usb_wrapper_dev_t *dev)
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{
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REG_WRITE_FIELD(dev, SS_PHY_CTRL, SS_PHY_RESET, 1);
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/* per HPG */
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udelay(10);
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REG_WRITE_FIELD(dev, SS_PHY_CTRL, SS_PHY_RESET, 0);
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}
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/* configure SS phy as specified in HPG */
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void usb_wrapper_ss_phy_configure(usb_wrapper_dev_t *dev)
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{
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/* 4.a */
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REG_WRITE_FIELD(dev, SS_PHY_CTRL, REF_USE_PAD, 1);
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/* .b */
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REG_WRITE_FIELD(dev, SS_PHY_CTRL, LANE0_PWR_PRESENT, 1);
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/* .c */
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REG_WRITE_FIELD(dev, SS_PHY_CTRL, REF_SS_PHY_EN, 1);
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/* For Aragorn V1, reset value fix is required.*/
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if ( (board_platform_id() == MSM8974) &&
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(board_soc_version() < BOARD_SOC_VERSION2))
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{
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REG_WRITE_FIELD(dev, SS_PHY_CTRL, SSC_REF_CLK_SEL, 0x108);
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}
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}
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/* configure SS phy electrical params */
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void usb_wrapper_ss_phy_electrical_config(usb_wrapper_dev_t *dev)
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{
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/* reset value seems to work just fine for now. */
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}
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/* Initialize HS phy */
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void usb_wrapper_hs_phy_init(usb_wrapper_dev_t *dev)
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{
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/* 5.a */
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REG_WRITE_FIELD(dev, HS_PHY_CTRL, FREECLK_SEL, 0x0);
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/* 5.b */
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REG_WRITE_FIELD(dev, HS_PHY_CTRL, COMMONONN, 0x1);
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}
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/* configure HS phy as specified in HPG */
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void usb_wrapper_hs_phy_configure(usb_wrapper_dev_t *dev)
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{
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/* 6.a */
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REG_WRITE(dev, PARAMETER_OVERRIDE_X, 0xD190E4);
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}
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void usb_wrapper_workaround_10(usb_wrapper_dev_t *dev)
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{
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/* 10. */
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if ( (board_platform_id() == MSM8974) &&
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(board_soc_version() < BOARD_SOC_VERSION2))
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{
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REG_WRITE(dev, GENERAL_CFG, 0x78);
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}
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}
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void usb_wrapper_workaround_11(usb_wrapper_dev_t *dev)
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{
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/*
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* 11. Apply WA for QCTDD00335018 -
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* a. Description: Enables the Tx for alt bus mode, powers up the pmos_bias block, and so on; required if manually running the alt bus features.
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* b. Assert LANE0.TX_ALT_BLOCK (102D) EN_ALT_BUS (bit 7);
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* c. To be replaced in V2 with other WA (which will be applied during suspend sequence)
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*
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*/
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/* Not implemented. required if manually running the alt bus features.*/
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}
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/* workaround #13 as described in HPG */
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void usb_wrapper_workaround_13(usb_wrapper_dev_t *dev)
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{
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REG_WRITE_FIELD(dev, SS_PHY_PARAM_CTRL_1, LOS_BIAS, 0x5);
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}
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void usb_wrapper_vbus_override(usb_wrapper_dev_t *dev)
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{
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/* set extenal vbus valid select */
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REG_WRITE_FIELD(dev, HS_PHY_CTRL_COMMON, VBUSVLDEXTSEL0, 0x1);
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/* enable D+ pullup */
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REG_WRITE_FIELD(dev, HS_PHY_CTRL, VBUSVLDEXT0, 0x1);
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/* set otg vbus valid from hs phy to controller */
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REG_WRITE_FIELD(dev, HS_PHY_CTRL, UTMI_OTG_VBUS_VALID, 0x1);
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/* Indicate value is driven by UTMI_OTG_VBUS_VALID bit */
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REG_WRITE_FIELD(dev, HS_PHY_CTRL, SW_SESSVLD_SEL, 0x1);
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/* Indicate power present to SS phy */
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if (!use_hsonly_mode())
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REG_WRITE_FIELD(dev, SS_PHY_CTRL, LANE0_PWR_PRESENT, 0x1);
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}
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/* API to read SS PHY registers */
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uint16_t usb_wrapper_ss_phy_read(usb_wrapper_dev_t *dev, uint16_t addr)
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{
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uint16_t data;
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/* write address to be read */
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REG_WRITE(dev, SS_CR_PROTOCOL_DATA_IN, addr);
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/* trigger capture of address in addr reg and wait until done */
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REG_WRITE(dev, SS_CR_PROTOCOL_CAP_ADDR, 0x1);
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while(REG_READ(dev, SS_CR_PROTOCOL_CAP_ADDR) & 0x1);
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/* read from referenced register */
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REG_WRITE(dev, SS_CR_PROTOCOL_READ, 0x1);
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/* wait until read is done */
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while(REG_READ(dev, SS_CR_PROTOCOL_READ) & 0x1);
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data = REG_READ(dev, SS_CR_PROTOCOL_DATA_OUT);
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/* TODO: hpg 4.14.2 note: reading ss phy register must be performed twice.
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* does this whole sequence need to be done twice or just the reading from
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* data_out??
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* QCTDD00516153
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*/
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ASSERT(0);
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return data;
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}
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/* API to write to SS PHY registers */
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void usb_wrapper_ss_phy_write(usb_wrapper_dev_t *dev, uint16_t addr, uint16_t data)
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{
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/* write address to be read */
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REG_WRITE(dev, SS_CR_PROTOCOL_DATA_IN, addr);
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/* trigger capture of address in addr reg and wait until done */
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REG_WRITE(dev, SS_CR_PROTOCOL_CAP_ADDR, 0x1);
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while(REG_READ(dev, SS_CR_PROTOCOL_CAP_ADDR) & 0x1);
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/* write address to be read */
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REG_WRITE(dev, SS_CR_PROTOCOL_DATA_IN, data);
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/* trigger capture of data in addr reg and wait until done */
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REG_WRITE(dev, SS_CR_PROTOCOL_CAP_DATA, 0x1);
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while(REG_READ(dev, SS_CR_PROTOCOL_CAP_DATA) & 0x1);
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/* write to referenced register and wait until done */
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REG_WRITE(dev, SS_CR_PROTOCOL_WRITE, 0x1);
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while(REG_READ(dev, SS_CR_PROTOCOL_READ) & 0x1);
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/* TODO: hpg 4.14.2 note: reading ss phy register must be performed twice.
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* does this whole sequence need to be done twice or just the reading from
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* data_out??
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* QCTDD00516153
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*/
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ASSERT(0);
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}
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/* initialize the wrapper core */
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usb_wrapper_dev_t * usb_wrapper_init(usb_wrapper_config_t *config)
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{
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usb_wrapper_dev_t *wrapper;
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/* create a wrapper device */
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wrapper = (usb_wrapper_dev_t*) malloc(sizeof(usb_wrapper_dev_t));
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ASSERT(wrapper);
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/* save qscratch base */
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wrapper->base = config->qscratch_base;
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/* HPG: section 4.4.1 Control sequence */
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usb_wrapper_dbm_mode(wrapper, DBM_MODE_BYPASS);
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/* HPG: section 4.4.1: use config 0 - all of RAM1 */
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usb_wrapper_ram_configure(wrapper);
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return wrapper;
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}
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void usb_wrapper_hs_phy_ctrl_force_write(usb_wrapper_dev_t *dev)
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{
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REG_WRITE(dev, HS_PHY_CTRL_COMMON, 0x00001CB8);
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}
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void usb_wrapper_hsonly_mode(usb_wrapper_dev_t *dev)
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{
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REG_WRITE_FIELD(dev, GENERAL_CFG, PIPE_UTMI_CLK_DIS, 0x1);
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udelay(1);
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REG_WRITE_FIELD(dev, GENERAL_CFG, PIPE_UTMI_CLK_SEL, 0x1);
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REG_WRITE_FIELD(dev, GENERAL_CFG, PIPE3_PHYSTATUS_SW, 0x1);
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udelay(1);
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REG_WRITE_FIELD(dev, GENERAL_CFG, PIPE_UTMI_CLK_DIS, 0x0);
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}
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