146 lines
4.4 KiB
C
146 lines
4.4 KiB
C
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Fundation, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <reg.h>
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#include <bits.h>
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#include <debug.h>
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#include <arch/arm.h>
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#include <arch/defines.h>
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#include <qtimer.h>
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#include <qgic_v3.h>
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#define GIC_WAKER_PROCESSORSLEEP BIT(1)
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#define GIC_WAKER_CHILDRENASLEEP BIT(2)
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void qgic_dist_init()
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{
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uint32_t num_irq;
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uint32_t affinity;
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uint32_t i;
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/* Read the mpidr register to find out the boot up cluster */
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__asm__ volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (affinity));
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/* For aarch32 mode we have only 3 affinity values: aff0:aff1:aff2*/
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affinity = affinity & 0x00ffffff;
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writel(0, GIC_DIST_CTRL);
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/*
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* Find out how many interrupts are supported.
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*/
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num_irq = readl(GIC_DIST_CTR) & 0x1f;
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num_irq = (num_irq + 1) * 32;
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/* Do the qgic dist initialization */
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qgic_dist_config(num_irq);
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/* Write the affinity value, for routing all the SPIs */
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for (i = 32; i < num_irq; i++)
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writel(affinity, GICD_IROUTER + i * 8);
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/* Enable affinity routing of grp0/grp1 interrupts */
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writel(ENABLE_GRP0_SEC | ENABLE_GRP1_NS | ENABLE_ARE, GIC_DIST_CTRL);
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}
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void qgic_cpu_init()
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{
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uint32_t retry = 1000;
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uint32_t sre = 0;
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uint32_t pmr = 0xff;
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uint32_t eoimode = 0;
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uint32_t grpen1 = 0x1;
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/* For cpu init need to wake up the redistributor */
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writel((readl(GICR_WAKER_CPU0) & ~GIC_WAKER_PROCESSORSLEEP), GICR_WAKER_CPU0);
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/* Wait until redistributor is up */
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while(readl(GICR_WAKER_CPU0) & GIC_WAKER_CHILDRENASLEEP)
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{
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retry--;
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if (!retry)
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{
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dprintf(CRITICAL, "Failed to wake redistributor for CPU0\n");
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ASSERT(0);
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}
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mdelay(1);
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}
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/* Make sure the system register access is enabled for us */
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__asm__ volatile("mrc p15, 0, %0, c12, c12, 5" : "=r" (sre));
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sre |= BIT(0);
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__asm__ volatile("mcr p15, 0, %0, c12, c12, 5" :: "r" (sre));
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isb();
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/* If system register access is not set, we fail */
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__asm__ volatile("mrc p15, 0, %0, c12, c12, 5" : "=r" (sre));
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if (!(sre & BIT(0)))
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{
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dprintf(CRITICAL, "Failed to set SRE for NS world\n");
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ASSERT(0);
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}
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/* Set the priortiy mask register, interrupts with priority
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* higher than this value will be signalled to processor.
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* Lower value means higher priority.
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*/
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__asm__ volatile("mcr p15, 0, %0, c4, c6, 0" :: "r" (pmr));
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isb();
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/* Make sure EOI is handled in NS EL3 */
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__asm__ volatile("mrc p15, 0, %0, c12, c12, 4" : "=r" (eoimode));
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eoimode &= ~BIT(1);
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__asm__ volatile("mcr p15, 0, %0, c12, c12, 4" :: "r" (eoimode));
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isb();
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/* Enable grp1 interrupts for NS EL3*/
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__asm__ volatile("mcr p15, 0, %0, c12, c12, 7" :: "r" (grpen1));
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isb();
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}
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uint32_t qgic_read_iar()
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{
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uint32_t iar;
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/* Read the interrupt ack register, for the current interrupt number */
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__asm__ volatile("mrc p15, 0, %0, c12, c12, 0" : "=r" (iar));
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isb();
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return iar;
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}
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void qgic_write_eoi(uint32_t iar)
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{
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/* Write end of interrupt to indicate CPU that this interrupt is processed*/
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__asm__ volatile("mcr p15, 0, %0, c12, c12, 1" :: "r" (iar));
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isb();
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}
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