62 lines
2.7 KiB
C
62 lines
2.7 KiB
C
/*
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* Copyright (c) 2011, 2014, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_MSM_SHARED_QGIC_H
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#define __PLATFORM_MSM_SHARED_QGIC_H
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#include "qgic_common.h"
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#include <platform/iomap.h>
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#include <platform/interrupts.h>
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#include <arch/arm.h>
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#define GIC_CPU_REG(off) (MSM_GIC_CPU_BASE + (off))
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#define GIC_CPU_CTRL GIC_CPU_REG(0x00)
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#define GIC_CPU_PRIMASK GIC_CPU_REG(0x04)
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#define GIC_CPU_BINPOINT GIC_CPU_REG(0x08)
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#define GIC_CPU_INTACK GIC_CPU_REG(0x0c)
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#define GIC_CPU_EOI GIC_CPU_REG(0x10)
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#define GIC_CPU_RUNNINGPRI GIC_CPU_REG(0x14)
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#define GIC_CPU_HIGHPRI GIC_CPU_REG(0x18)
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#define INTERRUPT_LVL_N_TO_N 0x0
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#define INTERRUPT_LVL_1_TO_N 0x1
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#define INTERRUPT_EDGE_N_TO_N 0x2
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#define INTERRUPT_EDGE_1_TO_N 0x3
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uint32_t qgic_read_iar(void);
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void qgic_write_eoi(uint32_t);
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enum handler_return gic_platform_irq(struct arm_iframe *frame);
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void gic_platform_fiq(struct arm_iframe *frame);
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status_t gic_mask_interrupt(unsigned int vector);
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status_t gic_unmask_interrupt(unsigned int vector);
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void gic_register_int_handler(unsigned int vector, int_handler func, void *arg);
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#endif
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