257 lines
6.1 KiB
C
257 lines
6.1 KiB
C
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "edp.h"
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#include "mdp5.h"
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#define RGB_COMPONENTS 3
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#define MAX_NUMBER_EDP_LANES 4
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struct edp_aux_ctrl edpctrl;
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static struct msm_panel_info *edp_pinfo;
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static void edp_config_ctrl(void)
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{
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struct edp_aux_ctrl *ep;
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struct dpcd_cap *cap;
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struct display_timing_desc *dp;
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unsigned long data = 0;
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ep = &edpctrl;
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dp = &ep->edid.timing[0];
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cap = &ep->dpcd;
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data = cap->max_lane_count - 1;
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data <<= 4;
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if (cap->enhanced_frame)
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data |= 0x40;
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if (ep->edid.color_depth == 8) {
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/* 0 == 6 bits, 1 == 8 bits */
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data |= 0x100; /* bit 8 */
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}
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if (!dp->interlaced) /* progressive */
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data |= 0x04;
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data |= 0x03; /* sycn clock & static Mvid */
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dprintf(SPEW, "%s: data=%x\n", __func__, data);
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edp_write(EDP_BASE + 0xc, data); /* EDP_CONFIGURATION_CTRL */
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}
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static void edp_config_sw_mvid_nvid(void)
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{
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edp_write(EDP_BASE + 0x14, 0x13b); /* EDP_SOFTWARE_MVID */
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edp_write(EDP_BASE + 0x18, 0x266); /* EDP_SOFTWARE_NVID */
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}
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void edp_clock_synchrous(void)
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{
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struct edp_aux_ctrl *ep;
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unsigned long data;
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unsigned long color;
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ep = &edpctrl;
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data = 1; /* sync */
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/* only legacy rgb mode supported */
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color = 0; /* 6 bits */
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if (ep->edid.color_depth == 8)
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color = 0x01;
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else if (ep->edid.color_depth == 10)
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color = 0x02;
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else if (ep->edid.color_depth == 12)
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color = 0x03;
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else if (ep->edid.color_depth == 16)
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color = 0x04;
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color <<= 5; /* bit 5 to bit 7 */
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data |= color;
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dprintf(SPEW, "%s: data=%x\n", __func__, data);
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/* EDP_MISC1_MISC0 */
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edp_write(EDP_BASE + 0x2c, data);
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}
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static void edp_config_tu(void)
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{
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/* temporary */
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edp_write(EDP_BASE + 0x160, 0x2b);
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edp_write(EDP_BASE + 0x15c, 0x00320033);
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edp_write(EDP_BASE + 0x34, 0x0023001a);
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}
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static void edp_config_timing(struct msm_panel_info *pinfo)
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{
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unsigned long total_ver, total_hor;
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unsigned long data;
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dprintf(INFO, "%s: width=%d hporch= %d %d %d\n", __func__,
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pinfo->xres, pinfo->lcdc.h_back_porch,
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pinfo->lcdc.h_front_porch, pinfo->lcdc.h_pulse_width);
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dprintf(INFO, "%s: height=%d vporch= %d %d %d\n", __func__,
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pinfo->yres, pinfo->lcdc.v_back_porch,
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pinfo->lcdc.v_front_porch, pinfo->lcdc.v_pulse_width);
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total_hor = pinfo->xres + pinfo->lcdc.h_back_porch +
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pinfo->lcdc.h_front_porch + pinfo->lcdc.h_pulse_width;
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total_ver = pinfo->yres + pinfo->lcdc.v_back_porch +
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pinfo->lcdc.v_front_porch + pinfo->lcdc.v_pulse_width;
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data = total_ver;
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data <<= 16;
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data |= total_hor;
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edp_write(EDP_BASE + 0x1c, data); /* EDP_TOTAL_HOR_VER */
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data = (pinfo->lcdc.v_back_porch + pinfo->lcdc.v_pulse_width);
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data <<= 16;
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data |= (pinfo->lcdc.h_back_porch + pinfo->lcdc.h_pulse_width);
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edp_write(EDP_BASE + 0x20, data); /* EDP_START_HOR_VER_FROM_SYNC */
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data = pinfo->lcdc.v_pulse_width;
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data <<= 16;
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data |= pinfo->lcdc.h_pulse_width;
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edp_write(EDP_BASE + 0x24, data); /* EDP_HSYNC_VSYNC_WIDTH_POLARITY */
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data = pinfo->yres;
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data <<= 16;
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data |= pinfo->xres;
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edp_write(EDP_BASE + 0x28, data); /* EDP_ACTIVE_HOR_VER */
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}
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static void edp_enable(int enable)
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{
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edp_write(EDP_BASE + 0x8, 0x0); /* EDP_STATE_CTRL */
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edp_write(EDP_BASE + 0x8, 0x40); /* EDP_STATE_CTRL */
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edp_write(EDP_BASE + 0x4, 0x01); /* EDP_MAINLINK_CTRL */
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}
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static void edp_disable(int enable)
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{
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edp_write(EDP_BASE + 0x8, 0x0); /* EDP_STATE_CTRL */
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edp_write(EDP_BASE + 0x4, 0x00); /* EDP_MAINLINK_CTRL */
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}
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int edp_on(void)
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{
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mdss_edp_pll_configure();
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mdss_edp_phy_pll_ready();
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edp_phy_vm_pe_init();
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edp_config_ctrl();
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edp_config_sw_mvid_nvid();
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edp_clock_synchrous();
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edp_config_timing(edp_pinfo);
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edp_config_tu();
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edp_config_clk();
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mdss_edp_lane_power_ctrl(1);
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edp_enable_mainlink(1);
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mdss_edp_link_train();
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edp_enable(1);
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mdss_edp_wait_for_video_ready();
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mdss_edp_irq_disable();
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dprintf(SPEW, "%s:\n", __func__);
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return 0;
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}
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int edp_off(void)
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{
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mdss_edp_irq_disable();
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edp_enable_mainlink(0);
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edp_phy_pll_reset();
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edp_mainlink_reset();
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edp_aux_reset();
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edp_disable(1);
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edp_unconfig_clk();
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mdss_edp_lane_power_ctrl(0);
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edp_phy_powerup(0);
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dprintf(SPEW, "%s:\n", __func__);
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return 0;
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}
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int edp_prepare(void)
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{
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mdss_edp_aux_init();
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edp_phy_pll_reset();
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edp_mainlink_reset();
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edp_aux_reset();
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edp_phy_powerup(1);
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edp_aux_enable();
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mdss_edp_irq_enable();
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mdss_edp_wait_for_hpd();
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mdss_edp_edid_read();
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mdss_edp_dpcd_cap_read();
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edp_edid2pinfo(edp_pinfo);
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edp_cap2pinfo(edp_pinfo);
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dprintf(SPEW, "%s:\n", __func__);
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return 0;
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}
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void edp_panel_init(struct msm_panel_info *pinfo)
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{
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if (!pinfo)
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return;
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pinfo->lcdc.dual_pipe = 0;
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pinfo->lcdc.split_display = 0;
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edp_pinfo = pinfo;
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edp_pinfo->on = edp_on;
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edp_pinfo->off = edp_off;
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edp_pinfo->prepare = edp_prepare;
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}
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