616 lines
14 KiB
C
616 lines
14 KiB
C
/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdint.h>
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#include <debug.h>
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#include <reg.h>
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#include <mmc.h>
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#include <clock.h>
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#include <pm8x41.h>
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#include <platform/clock.h>
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#include <platform/iomap.h>
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#include <platform/timer.h>
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#include <rpm-smd.h>
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#include <regulator.h>
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#include <platform.h>
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#define RPM_CE_CLK_TYPE 0x6563
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#define CE2_CLK_ID 0x1
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#define RPM_SMD_KEY_RATE 0x007A484B
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#define MAX_LOOPS 500
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uint32_t CE2_CLK[][8]=
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{
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{
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RPM_CE_CLK_TYPE, CE2_CLK_ID,
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KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
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RPM_SMD_KEY_RATE, 4, 0,
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},
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{
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RPM_CE_CLK_TYPE, CE2_CLK_ID,
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KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
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RPM_SMD_KEY_RATE, 4, 176128,
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},
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};
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void hsusb_clock_init(void)
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{
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int ret;
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struct clk *iclk, *cclk;
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ret = clk_get_set_enable("usb_iface_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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/* Wait for the clocks to be stable since we are disabling soon after. */
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mdelay(1);
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iclk = clk_get("usb_iface_clk");
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cclk = clk_get("usb_core_clk");
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clk_disable(iclk);
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clk_disable(cclk);
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/* Wait for the clock disable to complete. */
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mdelay(1);
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/* Start the block reset for usb */
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writel(1, USB_HS_BCR);
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/* Wait for reset to complete. */
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mdelay(1);
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/* Take usb block out of reset */
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writel(0, USB_HS_BCR);
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/* Wait for the block to be brought out of reset. */
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mdelay(1);
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ret = clk_enable(iclk);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_enable(cclk);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret);
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ASSERT(0);
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}
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}
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void clock_init_mmc(uint32_t interface)
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{
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char clk_name[64];
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int ret;
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snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface);
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/* enable interface clock */
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set sdc%u_iface_clk ret = %d\n", interface, ret);
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ASSERT(0);
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}
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}
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/* Configure MMC clock */
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void clock_config_mmc(uint32_t interface, uint32_t freq)
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{
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int ret = 0;
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char clk_name[64];
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snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
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if(freq == MMC_CLK_400KHZ)
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{
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ret = clk_get_set_enable(clk_name, 400000, 1);
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}
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else if(freq == MMC_CLK_50MHZ)
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{
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ret = clk_get_set_enable(clk_name, 50000000, 1);
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}
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else if(freq == MMC_CLK_96MHZ)
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{
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ret = clk_get_set_enable(clk_name, 100000000, 1);
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}
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else if(freq == MMC_CLK_192MHZ)
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{
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if (platform_is_msm8992())
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ret = clk_get_set_enable(clk_name, 172000000, 1);
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else
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ret = clk_get_set_enable(clk_name, 192000000, 1);
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}
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else if(freq == MMC_CLK_200MHZ)
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{
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ret = clk_get_set_enable(clk_name, 200000000, 1);
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}
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else if(freq == MMC_CLK_400MHZ)
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{
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if (platform_is_msm8992())
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ret = clk_get_set_enable(clk_name, 344000000, 1);
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else
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ret = clk_get_set_enable(clk_name, 384000000, 1);
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}
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else
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{
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dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
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ASSERT(0);
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}
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if(ret)
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{
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dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret);
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ASSERT(0);
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}
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}
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/* Configure UART clock based on the UART block id*/
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void clock_config_uart_dm(uint8_t id)
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{
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int ret;
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char iclk[64];
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char cclk[64];
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snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
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snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
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ret = clk_get_set_enable(iclk, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable(cclk, 7372800, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret);
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ASSERT(0);
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}
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}
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/* Function to asynchronously reset CE (Crypto Engine).
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* Function assumes that all the CE clocks are off.
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*/
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static void ce_async_reset(uint8_t instance)
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{
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if (instance == 2)
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{
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/* Start the block reset for CE */
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writel(1, GCC_CE2_BCR);
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udelay(2);
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/* Take CE block out of reset */
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writel(0, GCC_CE2_BCR);
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udelay(2);
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}
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else
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{
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dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance);
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ASSERT(0);
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}
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}
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void clock_ce_enable(uint8_t instance)
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{
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if (instance == 2)
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rpm_send_data(&CE2_CLK[GENERIC_ENABLE][0], 24, RPM_REQUEST_TYPE);
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else
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{
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dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance);
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ASSERT(0);
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}
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}
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void clock_ce_disable(uint8_t instance)
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{
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if (instance == 2)
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rpm_send_data(&CE2_CLK[GENERIC_DISABLE][0], 24, RPM_REQUEST_TYPE);
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else
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{
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dprintf(CRITICAL, "Unsupported CE instance: %u\n", instance);
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ASSERT(0);
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}
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}
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void clock_config_ce(uint8_t instance)
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{
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/* Need to enable the clock before disabling since the clk_disable()
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* has a check to default to nop when the clk_enable() is not called
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* on that particular clock.
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*/
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clock_ce_enable(instance);
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clock_ce_disable(instance);
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ce_async_reset(instance);
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clock_ce_enable(instance);
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}
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void clock_usb30_gdsc_enable(void)
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{
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uint32_t reg = readl(GCC_USB30_GDSCR);
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reg &= ~(0x1);
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writel(reg, GCC_USB30_GDSCR);
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}
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/* enables usb30 clocks */
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void clock_usb30_init(void)
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{
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int ret;
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ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
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ASSERT(0);
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}
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clock_usb30_gdsc_enable();
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ret = clk_get_set_enable("usb30_master_clk", 125000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("usb30_phy_aux_clk", 1200000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb30_phy_aux_clk. ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("usb30_sleep_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret);
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ASSERT(0);
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}
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pm8x41_lnbb_clock_ctrl(1);
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}
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void clock_bumpup_pipe3_clk()
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{
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int ret = 0;
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ret = clk_get_set_enable("usb30_pipe_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
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ASSERT(0);
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}
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return;
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}
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void mdp_gdsc_ctrl(uint8_t enable)
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{
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uint32_t reg = 0;
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reg = readl(MDP_GDSCR);
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if (enable) {
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if (!(reg & GDSC_POWER_ON_BIT)) {
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reg &= ~(BIT(0) | GDSC_EN_FEW_WAIT_MASK);
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reg |= GDSC_EN_FEW_WAIT_256_MASK;
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writel(reg, MDP_GDSCR);
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while(!(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT)));
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} else {
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dprintf(INFO, "MDP GDSC already enabled\n");
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}
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} else {
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reg |= BIT(0);
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writel(reg, MDP_GDSCR);
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while(readl(MDP_GDSCR) & (GDSC_POWER_ON_BIT));
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}
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}
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/* Configure MDP clock */
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void mdp_clock_enable(void)
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{
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int ret;
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/* Set MDP clock to 240MHz */
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ret = clk_get_set_enable("mdp_ahb_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mdss_mdp_clk_src", 300000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdp_clk_src ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mdss_vsync_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdss vsync clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mdss_mdp_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdp_clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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void mdp_clock_disable()
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{
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clk_disable(clk_get("mdss_vsync_clk"));
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clk_disable(clk_get("mdss_mdp_clk"));
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clk_disable(clk_get("mdss_mdp_clk_src"));
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clk_disable(clk_get("mdp_ahb_clk"));
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}
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void mmss_bus_clock_enable(void)
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{
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int ret;
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/* Configure MMSSNOC AXI clock */
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ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 300000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mmssnoc_axi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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/* Configure S0 AXI clock */
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ret = clk_get_set_enable("mmss_s0_axi_clk", 300000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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/* Configure AXI clock */
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ret = clk_get_set_enable("mdss_axi_clk", 300000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdss_axi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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void mmss_bus_clock_disable(void)
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{
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/* Disable MDSS AXI clock */
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clk_disable(clk_get("mdss_axi_clk"));
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/* Disable MMSSNOC S0AXI clock */
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clk_disable(clk_get("mmss_s0_axi_clk"));
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/* Disable MMSSNOC AXI clock */
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clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
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}
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static void rcg_update_config(uint32_t reg)
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{
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int i;
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for (i = 0; i < MAX_LOOPS; i++) {
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if (!(readl(reg) & BIT(0)))
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return;
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udelay(1);
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}
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dprintf(CRITICAL, "failed to update rcg config for reg = 0x%x\n", reg);
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ASSERT(0);
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}
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static void branch_clk_halt_check(uint32_t reg)
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{
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int i;
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for (i = 0; i < MAX_LOOPS; i++) {
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if (!(readl(reg) & BIT(31)))
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return;
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udelay(1);
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}
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dprintf(CRITICAL, "failed to enable branch for reg = 0x%x\n", reg);
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ASSERT(0);
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}
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void mmss_dsi_clock_enable(uint32_t cfg_rcgr, uint32_t flags,
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uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
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{
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int ret;
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if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
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/* Enable DSI0 branch clocks */
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/* Set the source for DSI0 byte RCG */
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writel(cfg_rcgr, DSI_BYTE0_CFG_RCGR);
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/* Set the update RCG bit */
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writel(0x1, DSI_BYTE0_CMD_RCGR);
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rcg_update_config(DSI_BYTE0_CMD_RCGR);
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/* Enable the branch clock */
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writel(0x1, DSI_BYTE0_CBCR);
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branch_clk_halt_check(DSI_BYTE0_CBCR);
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/* Set the source for DSI0 pixel RCG */
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writel(cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
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/* Set the MND for DSI0 pixel clock */
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writel(pclk0_m, DSI_PIXEL0_M);
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writel(pclk0_n, DSI_PIXEL0_N);
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writel(pclk0_d, DSI_PIXEL0_D);
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/* Set the update RCG bit */
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writel(0x1, DSI_PIXEL0_CMD_RCGR);
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rcg_update_config(DSI_PIXEL0_CMD_RCGR);
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/* Enable the branch clock */
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writel(0x1, DSI_PIXEL0_CBCR);
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branch_clk_halt_check(DSI_PIXEL0_CBCR);
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ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
|
|
/* Enable DSI1 branch clocks */
|
|
|
|
/* Set the source for DSI1 byte RCG */
|
|
writel(cfg_rcgr, DSI_BYTE1_CFG_RCGR);
|
|
/* Set the update RCG bit */
|
|
writel(0x1, DSI_BYTE1_CMD_RCGR);
|
|
rcg_update_config(DSI_BYTE1_CMD_RCGR);
|
|
/* Enable the branch clock */
|
|
writel(0x1, DSI_BYTE1_CBCR);
|
|
branch_clk_halt_check(DSI_BYTE1_CBCR);
|
|
|
|
/* Set the source for DSI1 pixel RCG */
|
|
writel(cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
|
|
/* Set the MND for DSI1 pixel clock */
|
|
writel(pclk0_m, DSI_PIXEL1_M);
|
|
writel(pclk0_n, DSI_PIXEL1_N);
|
|
writel(pclk0_d, DSI_PIXEL1_D);
|
|
/* Set the update RCG bit */
|
|
writel(0x1, DSI_PIXEL1_CMD_RCGR);
|
|
rcg_update_config(DSI_PIXEL1_CMD_RCGR);
|
|
/* Enable the branch clock */
|
|
writel(0x1, DSI_PIXEL1_CBCR);
|
|
branch_clk_halt_check(DSI_PIXEL1_CBCR);
|
|
|
|
ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
|
|
if(ret)
|
|
{
|
|
dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
}
|
|
|
|
void mmss_dsi_clock_disable(uint32_t flags)
|
|
{
|
|
if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
|
|
clk_disable(clk_get("mdss_esc0_clk"));
|
|
writel(0x0, DSI_BYTE0_CBCR);
|
|
writel(0x0, DSI_PIXEL0_CBCR);
|
|
}
|
|
|
|
if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
|
|
clk_disable(clk_get("mdss_esc1_clk"));
|
|
writel(0x0, DSI_BYTE1_CBCR);
|
|
writel(0x0, DSI_PIXEL1_CBCR);
|
|
}
|
|
}
|
|
|
|
void hdmi_core_ahb_clk_enable(void)
|
|
{
|
|
int ret;
|
|
|
|
/* Configure hdmi ahb clock */
|
|
ret = clk_get_set_enable("hdmi_ahb_clk", 0, 1);
|
|
if(ret) {
|
|
dprintf(CRITICAL, "failed to set hdmi_ahb_clk ret = %d\n", ret);
|
|
ASSERT(0);
|
|
}
|
|
|
|
/* Configure hdmi core clock */
|
|
ret = clk_get_set_enable("hdmi_core_clk", 19200000, 1);
|
|
if(ret) {
|
|
dprintf(CRITICAL, "failed to set hdmi_core_clk ret = %d\n", ret);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
void hdmi_pixel_clk_enable(uint32_t rate)
|
|
{
|
|
int ret;
|
|
|
|
/* Configure hdmi pixel clock */
|
|
ret = clk_get_set_enable("hdmi_extp_clk", rate, 1);
|
|
if(ret) {
|
|
dprintf(CRITICAL, "failed to set hdmi_extp_clk ret = %d\n", ret);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
void hdmi_pixel_clk_disable(void)
|
|
{
|
|
clk_disable(clk_get("hdmi_extp_clk"));
|
|
}
|
|
|
|
void hdmi_core_ahb_clk_disable(void)
|
|
{
|
|
clk_disable(clk_get("hdmi_core_clk"));
|
|
clk_disable(clk_get("hdmi_ahb_clk"));
|
|
}
|