238 lines
6.5 KiB
C
238 lines
6.5 KiB
C
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <reg.h>
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#include <platform/iomap.h>
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#include <qgic.h>
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#include <qtimer.h>
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#include <mmu.h>
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#include <arch/arm/mmu.h>
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#include <smem.h>
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#include <target/display.h>
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#define MB (1024*1024)
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#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
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#define A7_SS_SIZE ((A7_SS_END - A7_SS_BASE)/MB)
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/* LK memory - cacheable, write back */
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#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
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MMU_MEMORY_AP_READ_WRITE)
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#define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
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MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
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/* Peripherals - non-shared device */
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#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
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MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
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/* IMEM memory - cacheable, write through */
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#define IMEM_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
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MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
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static mmu_section_t mmu_section_table[] = {
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/* Physical addr, Virtual addr, Size (in MB), Flags */
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{ MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
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{ MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
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{ A7_SS_BASE, A7_SS_BASE, A7_SS_SIZE, IOMAP_MEMORY},
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{ SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, IMEM_MEMORY},
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{ MSM_SHARED_BASE, MSM_SHARED_BASE, 1, COMMON_MEMORY},
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{ MIPI_FB_ADDR, MIPI_FB_ADDR, 10, COMMON_MEMORY},
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};
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static struct smem_ram_ptable ram_ptable;
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void platform_early_init(void)
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{
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board_init();
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platform_clock_init();
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qgic_init();
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qtimer_init();
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}
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void platform_init(void)
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{
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dprintf(INFO, "platform_init()\n");
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}
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void platform_uninit(void)
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{
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qtimer_uninit();
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if (!platform_boot_dev_isemmc())
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qpic_nand_uninit();
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}
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uint32_t platform_get_sclk_count(void)
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{
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return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
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}
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addr_t get_bs_info_addr()
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{
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return ((addr_t)BS_INFO_ADDR);
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}
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int platform_use_identity_mmu_mappings(void)
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{
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/* Use only the mappings specified in this file. */
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return 0;
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}
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/* Setup memory for this platform */
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void platform_init_mmu_mappings(void)
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{
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uint32_t i;
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uint32_t sections;
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uint32_t table_size = ARRAY_SIZE(mmu_section_table);
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ram_partition ptn_entry;
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uint32_t len = 0;
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ASSERT(smem_ram_ptable_init_v1());
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len = smem_get_ram_ptable_len();
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/* Configure the MMU page entries for SDRAM and IMEM memory read
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from the smem ram table*/
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for(i = 0; i < len; i++)
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{
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smem_get_ram_ptable_entry(&ptn_entry, i);
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if(ptn_entry.type == SYS_MEMORY)
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{
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if((ptn_entry.category == SDRAM) ||
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(ptn_entry.category == IMEM))
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{
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/* Check to ensure that start address is 1MB aligned */
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ASSERT((ptn_entry.start & (MB-1)) == 0);
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sections = (ptn_entry.size) / MB;
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while(sections--)
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{
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arm_mmu_map_section(ptn_entry.start +
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sections * MB,
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ptn_entry.start +
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sections * MB,
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(MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
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MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
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}
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}
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}
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}
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/* Configure the MMU page entries for memory read from the
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mmu_section_table */
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for (i = 0; i < table_size; i++)
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{
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sections = mmu_section_table[i].num_of_sections;
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while (sections--)
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{
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arm_mmu_map_section(mmu_section_table[i].paddress +
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sections * MB,
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mmu_section_table[i].vaddress +
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sections * MB,
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mmu_section_table[i].flags);
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}
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}
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}
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addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
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{
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/* Using 1-1 mapping on this platform. */
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return virt_addr;
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}
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addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
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{
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/* Using 1-1 mapping on this platform. */
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return phys_addr;
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}
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/* DYNAMIC SMEM REGION feature enables LK to dynamically
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* read the SMEM addr info from TCSR_TZ_WONCE register.
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* The first word read, if indicates a MAGIC number, then
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* Dynamic SMEM is assumed to be enabled. Read the remaining
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* SMEM info for SMEM Size and Phy_addr from the other bytes.
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*/
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uint32_t platform_get_smem_base_addr()
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{
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struct smem_addr_info *smem_info = NULL;
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smem_info = (struct smem_addr_info *)readl(TCSR_TZ_WONCE);
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if(smem_info && (smem_info->identifier == SMEM_TARGET_INFO_IDENTIFIER))
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return smem_info->phy_addr;
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else
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return MSM_SHARED_BASE;
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}
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int platform_is_msm8909()
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{
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uint32_t platform = board_platform_id();
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uint32_t ret = 0;
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switch(platform)
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{
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case MSM8909:
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case MSM8209:
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case MSM8208:
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case APQ8009:
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case MSM8609:
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ret = 1;
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break;
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default:
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ret = 0;
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};
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return ret;
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}
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int boot_device_mask(int val)
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{
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return ((val & 0x0E) >> 1);
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}
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uint32_t platform_detect_panel()
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{
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uint32_t panel;
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/* Bits 28:29 of this register are read to know
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the panel config, and pick up DT accordingly.
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00 -no limit, suport HD
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01 - limit to 720P
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10- limit to qHD
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11- limit to fWVGA
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*/
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panel = readl(SECURITY_CONTROL_CORE_FEATURE_CONFIG0);
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panel = (panel & 0x30000000) >> 28;
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return panel;
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}
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