56 lines
2.5 KiB
C
56 lines
2.5 KiB
C
//------------------------------------------------------------------------------
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// ISC License (ISC)
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//
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// Copyright (c) 2005-2010, The Linux Foundation
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// All rights reserved.
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// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
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//
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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//
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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//
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//
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//------------------------------------------------------------------------------
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//==============================================================================
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// Author(s): ="Atheros"
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//==============================================================================
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#define AR6001_GPIO_PIN_COUNT 18
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#define AR6002_GPIO_PIN_COUNT 18
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#define AR6003_GPIO_PIN_COUNT 28
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#define MCKINLEY_GPIO_PIN_COUNT 57
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/*
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* Values of gpioreg_id in the WMIX_GPIO_REGISTER_SET_CMDID and WMIX_GPIO_REGISTER_GET_CMDID
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* commands come in two flavors. If the upper bit of gpioreg_id is CLEAR, then the
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* remainder is interpreted as one of these values. This provides platform-independent
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* access to GPIO registers. If the upper bit (GPIO_ID_OFFSET_FLAG) of gpioreg_id is SET,
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* then the remainder is interpreted as a platform-specific GPIO register offset.
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*/
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#define GPIO_ID_OUT 0x00000000
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#define GPIO_ID_OUT_W1TS 0x00000001
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#define GPIO_ID_OUT_W1TC 0x00000002
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#define GPIO_ID_ENABLE 0x00000003
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#define GPIO_ID_ENABLE_W1TS 0x00000004
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#define GPIO_ID_ENABLE_W1TC 0x00000005
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#define GPIO_ID_IN 0x00000006
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#define GPIO_ID_STATUS 0x00000007
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#define GPIO_ID_STATUS_W1TS 0x00000008
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#define GPIO_ID_STATUS_W1TC 0x00000009
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#define GPIO_ID_PIN0 0x0000000a
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#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
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#define GPIO_ID_NONE 0xffffffff
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#define GPIO_ID_OFFSET_FLAG 0x80000000
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#define GPIO_ID_REG_MASK 0x7fffffff
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#define GPIO_ID_IS_OFFSET(reg_id) (((reg_id) & GPIO_ID_OFFSET_FLAG) != 0)
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