435 lines
9.2 KiB
C
435 lines
9.2 KiB
C
/*
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* Definitions for the NVM Express interface
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* Copyright (c) 2011, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef _LINUX_NVME_H
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#define _LINUX_NVME_H
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#include <linux/types.h>
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struct nvme_bar {
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__u64 cap; /* Controller Capabilities */
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__u32 vs; /* Version */
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__u32 intms; /* Interrupt Mask Set */
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__u32 intmc; /* Interrupt Mask Clear */
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__u32 cc; /* Controller Configuration */
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__u32 rsvd1; /* Reserved */
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__u32 csts; /* Controller Status */
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__u32 rsvd2; /* Reserved */
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__u32 aqa; /* Admin Queue Attributes */
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__u64 asq; /* Admin SQ Base Address */
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__u64 acq; /* Admin CQ Base Address */
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};
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#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
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#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
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enum {
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NVME_CC_ENABLE = 1 << 0,
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NVME_CC_CSS_NVM = 0 << 4,
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NVME_CC_MPS_SHIFT = 7,
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NVME_CC_ARB_RR = 0 << 11,
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NVME_CC_ARB_WRRU = 1 << 11,
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NVME_CC_ARB_VS = 7 << 11,
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NVME_CC_SHN_NONE = 0 << 14,
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NVME_CC_SHN_NORMAL = 1 << 14,
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NVME_CC_SHN_ABRUPT = 2 << 14,
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NVME_CC_IOSQES = 6 << 16,
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NVME_CC_IOCQES = 4 << 20,
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NVME_CSTS_RDY = 1 << 0,
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NVME_CSTS_CFS = 1 << 1,
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NVME_CSTS_SHST_NORMAL = 0 << 2,
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NVME_CSTS_SHST_OCCUR = 1 << 2,
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NVME_CSTS_SHST_CMPLT = 2 << 2,
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};
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struct nvme_id_power_state {
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__le16 max_power; /* centiwatts */
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__u16 rsvd2;
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__le32 entry_lat; /* microseconds */
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__le32 exit_lat; /* microseconds */
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__u8 read_tput;
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__u8 read_lat;
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__u8 write_tput;
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__u8 write_lat;
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__u8 rsvd16[16];
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};
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#define NVME_VS(major, minor) (major << 16 | minor)
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struct nvme_id_ctrl {
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__le16 vid;
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__le16 ssvid;
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char sn[20];
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char mn[40];
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char fr[8];
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__u8 rab;
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__u8 ieee[3];
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__u8 mic;
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__u8 mdts;
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__u8 rsvd78[178];
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__le16 oacs;
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__u8 acl;
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__u8 aerl;
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__u8 frmw;
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__u8 lpa;
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__u8 elpe;
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__u8 npss;
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__u8 rsvd264[248];
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__u8 sqes;
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__u8 cqes;
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__u8 rsvd514[2];
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__le32 nn;
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__le16 oncs;
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__le16 fuses;
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__u8 fna;
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__u8 vwc;
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__le16 awun;
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__le16 awupf;
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__u8 rsvd530[1518];
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struct nvme_id_power_state psd[32];
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__u8 vs[1024];
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};
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struct nvme_lbaf {
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__le16 ms;
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__u8 ds;
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__u8 rp;
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};
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struct nvme_id_ns {
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__le64 nsze;
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__le64 ncap;
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__le64 nuse;
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__u8 nsfeat;
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__u8 nlbaf;
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__u8 flbas;
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__u8 mc;
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__u8 dpc;
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__u8 dps;
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__u8 rsvd30[98];
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struct nvme_lbaf lbaf[16];
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__u8 rsvd192[192];
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__u8 vs[3712];
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};
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enum {
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NVME_NS_FEAT_THIN = 1 << 0,
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NVME_LBAF_RP_BEST = 0,
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NVME_LBAF_RP_BETTER = 1,
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NVME_LBAF_RP_GOOD = 2,
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NVME_LBAF_RP_DEGRADED = 3,
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};
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struct nvme_lba_range_type {
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__u8 type;
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__u8 attributes;
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__u8 rsvd2[14];
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__u64 slba;
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__u64 nlb;
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__u8 guid[16];
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__u8 rsvd48[16];
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};
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enum {
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NVME_LBART_TYPE_FS = 0x01,
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NVME_LBART_TYPE_RAID = 0x02,
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NVME_LBART_TYPE_CACHE = 0x03,
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NVME_LBART_TYPE_SWAP = 0x04,
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NVME_LBART_ATTRIB_TEMP = 1 << 0,
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NVME_LBART_ATTRIB_HIDE = 1 << 1,
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};
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/* I/O commands */
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enum nvme_opcode {
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nvme_cmd_flush = 0x00,
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nvme_cmd_write = 0x01,
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nvme_cmd_read = 0x02,
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nvme_cmd_write_uncor = 0x04,
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nvme_cmd_compare = 0x05,
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nvme_cmd_dsm = 0x09,
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};
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struct nvme_common_command {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u32 cdw2[2];
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__le64 metadata;
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__le64 prp1;
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__le64 prp2;
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__u32 cdw10[6];
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};
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struct nvme_rw_command {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd2;
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__le64 metadata;
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__le64 prp1;
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__le64 prp2;
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__le64 slba;
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__le16 length;
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__le16 control;
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__le32 dsmgmt;
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__le32 reftag;
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__le16 apptag;
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__le16 appmask;
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};
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enum {
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NVME_RW_LR = 1 << 15,
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NVME_RW_FUA = 1 << 14,
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NVME_RW_DSM_FREQ_UNSPEC = 0,
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NVME_RW_DSM_FREQ_TYPICAL = 1,
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NVME_RW_DSM_FREQ_RARE = 2,
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NVME_RW_DSM_FREQ_READS = 3,
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NVME_RW_DSM_FREQ_WRITES = 4,
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NVME_RW_DSM_FREQ_RW = 5,
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NVME_RW_DSM_FREQ_ONCE = 6,
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NVME_RW_DSM_FREQ_PREFETCH = 7,
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NVME_RW_DSM_FREQ_TEMP = 8,
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NVME_RW_DSM_LATENCY_NONE = 0 << 4,
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NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
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NVME_RW_DSM_LATENCY_NORM = 2 << 4,
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NVME_RW_DSM_LATENCY_LOW = 3 << 4,
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NVME_RW_DSM_SEQ_REQ = 1 << 6,
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NVME_RW_DSM_COMPRESSED = 1 << 7,
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};
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/* Admin commands */
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enum nvme_admin_opcode {
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nvme_admin_delete_sq = 0x00,
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nvme_admin_create_sq = 0x01,
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nvme_admin_get_log_page = 0x02,
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nvme_admin_delete_cq = 0x04,
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nvme_admin_create_cq = 0x05,
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nvme_admin_identify = 0x06,
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nvme_admin_abort_cmd = 0x08,
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nvme_admin_set_features = 0x09,
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nvme_admin_get_features = 0x0a,
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nvme_admin_async_event = 0x0c,
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nvme_admin_activate_fw = 0x10,
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nvme_admin_download_fw = 0x11,
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nvme_admin_format_nvm = 0x80,
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nvme_admin_security_send = 0x81,
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nvme_admin_security_recv = 0x82,
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};
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enum {
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NVME_QUEUE_PHYS_CONTIG = (1 << 0),
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NVME_CQ_IRQ_ENABLED = (1 << 1),
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NVME_SQ_PRIO_URGENT = (0 << 1),
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NVME_SQ_PRIO_HIGH = (1 << 1),
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NVME_SQ_PRIO_MEDIUM = (2 << 1),
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NVME_SQ_PRIO_LOW = (3 << 1),
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NVME_FEAT_ARBITRATION = 0x01,
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NVME_FEAT_POWER_MGMT = 0x02,
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NVME_FEAT_LBA_RANGE = 0x03,
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NVME_FEAT_TEMP_THRESH = 0x04,
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NVME_FEAT_ERR_RECOVERY = 0x05,
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NVME_FEAT_VOLATILE_WC = 0x06,
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NVME_FEAT_NUM_QUEUES = 0x07,
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NVME_FEAT_IRQ_COALESCE = 0x08,
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NVME_FEAT_IRQ_CONFIG = 0x09,
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NVME_FEAT_WRITE_ATOMIC = 0x0a,
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NVME_FEAT_ASYNC_EVENT = 0x0b,
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NVME_FEAT_SW_PROGRESS = 0x0c,
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};
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struct nvme_identify {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd2[2];
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__le64 prp1;
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__le64 prp2;
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__le32 cns;
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__u32 rsvd11[5];
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};
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struct nvme_features {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__le32 nsid;
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__u64 rsvd2[2];
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__le64 prp1;
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__le64 prp2;
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__le32 fid;
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__le32 dword11;
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__u32 rsvd12[4];
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};
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struct nvme_create_cq {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__u32 rsvd1[5];
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__le64 prp1;
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__u64 rsvd8;
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__le16 cqid;
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__le16 qsize;
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__le16 cq_flags;
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__le16 irq_vector;
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__u32 rsvd12[4];
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};
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struct nvme_create_sq {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__u32 rsvd1[5];
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__le64 prp1;
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__u64 rsvd8;
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__le16 sqid;
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__le16 qsize;
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__le16 sq_flags;
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__le16 cqid;
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__u32 rsvd12[4];
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};
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struct nvme_delete_queue {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__u32 rsvd1[9];
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__le16 qid;
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__u16 rsvd10;
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__u32 rsvd11[5];
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};
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struct nvme_download_firmware {
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__u8 opcode;
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__u8 flags;
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__u16 command_id;
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__u32 rsvd1[5];
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__le64 prp1;
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__le64 prp2;
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__le32 numd;
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__le32 offset;
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__u32 rsvd12[4];
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};
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struct nvme_command {
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union {
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struct nvme_common_command common;
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struct nvme_rw_command rw;
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struct nvme_identify identify;
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struct nvme_features features;
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struct nvme_create_cq create_cq;
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struct nvme_create_sq create_sq;
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struct nvme_delete_queue delete_queue;
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struct nvme_download_firmware dlfw;
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};
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};
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enum {
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NVME_SC_SUCCESS = 0x0,
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NVME_SC_INVALID_OPCODE = 0x1,
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NVME_SC_INVALID_FIELD = 0x2,
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NVME_SC_CMDID_CONFLICT = 0x3,
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NVME_SC_DATA_XFER_ERROR = 0x4,
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NVME_SC_POWER_LOSS = 0x5,
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NVME_SC_INTERNAL = 0x6,
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NVME_SC_ABORT_REQ = 0x7,
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NVME_SC_ABORT_QUEUE = 0x8,
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NVME_SC_FUSED_FAIL = 0x9,
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NVME_SC_FUSED_MISSING = 0xa,
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NVME_SC_INVALID_NS = 0xb,
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NVME_SC_LBA_RANGE = 0x80,
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NVME_SC_CAP_EXCEEDED = 0x81,
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NVME_SC_NS_NOT_READY = 0x82,
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NVME_SC_CQ_INVALID = 0x100,
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NVME_SC_QID_INVALID = 0x101,
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NVME_SC_QUEUE_SIZE = 0x102,
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NVME_SC_ABORT_LIMIT = 0x103,
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NVME_SC_ABORT_MISSING = 0x104,
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NVME_SC_ASYNC_LIMIT = 0x105,
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NVME_SC_FIRMWARE_SLOT = 0x106,
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NVME_SC_FIRMWARE_IMAGE = 0x107,
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NVME_SC_INVALID_VECTOR = 0x108,
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NVME_SC_INVALID_LOG_PAGE = 0x109,
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NVME_SC_INVALID_FORMAT = 0x10a,
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NVME_SC_BAD_ATTRIBUTES = 0x180,
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NVME_SC_WRITE_FAULT = 0x280,
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NVME_SC_READ_ERROR = 0x281,
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NVME_SC_GUARD_CHECK = 0x282,
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NVME_SC_APPTAG_CHECK = 0x283,
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NVME_SC_REFTAG_CHECK = 0x284,
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NVME_SC_COMPARE_FAILED = 0x285,
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NVME_SC_ACCESS_DENIED = 0x286,
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};
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struct nvme_completion {
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__le32 result; /* Used by admin commands to return data */
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__u32 rsvd;
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__le16 sq_head; /* how much of this queue may be reclaimed */
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__le16 sq_id; /* submission queue that generated this entry */
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__u16 command_id; /* of the command which completed */
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__le16 status; /* did the command fail, and if so, why? */
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};
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struct nvme_user_io {
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__u8 opcode;
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__u8 flags;
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__u16 control;
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__u16 nblocks;
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__u16 rsvd;
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__u64 metadata;
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__u64 addr;
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__u64 slba;
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__u32 dsmgmt;
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__u32 reftag;
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__u16 apptag;
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__u16 appmask;
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};
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struct nvme_admin_cmd {
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__u8 opcode;
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__u8 flags;
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__u16 rsvd1;
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__u32 nsid;
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__u32 cdw2;
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__u32 cdw3;
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__u64 metadata;
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__u64 addr;
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__u32 metadata_len;
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__u32 data_len;
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__u32 cdw10;
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__u32 cdw11;
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__u32 cdw12;
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__u32 cdw13;
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__u32 cdw14;
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__u32 cdw15;
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__u32 timeout_ms;
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__u32 result;
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};
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#define NVME_IOCTL_ID _IO('N', 0x40)
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#define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
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#define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
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#endif /* _LINUX_NVME_H */
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