263 lines
11 KiB
C
263 lines
11 KiB
C
/*
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* Timer/Counter Unit (TC) registers.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef ATMEL_TC_H
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#define ATMEL_TC_H
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#include <linux/compiler.h>
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#include <linux/list.h>
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/*
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* Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
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* three general-purpose 16-bit timers. These timers share one register bank.
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* Depending on the SOC, each timer may have its own clock and IRQ, or those
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* may be shared by the whole TC block.
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*
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* These TC blocks may have up to nine external pins: TCLK0..2 signals for
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* clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
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* or triggering. Those pins need to be set up for use with the TC block,
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* else they will be used as GPIOs or for a different controller.
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*
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* Although we expect each TC block to have a platform_device node, those
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* nodes are not what drivers bind to. Instead, they ask for a specific
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* TC block, by number ... which is a common approach on systems with many
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* timers. Then they use clk_get() and platform_get_irq() to get clock and
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* IRQ resources.
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*/
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struct clk;
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/**
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* struct atmel_tcb_config - SoC data for a Timer/Counter Block
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* @counter_width: size in bits of a timer counter register
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*/
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struct atmel_tcb_config {
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size_t counter_width;
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};
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/**
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* struct atmel_tc - information about a Timer/Counter Block
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* @pdev: physical device
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* @iomem: resource associated with the I/O register
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* @regs: mapping through which the I/O registers can be accessed
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* @tcb_config: configuration data from SoC
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* @irq: irq for each of the three channels
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* @clk: internal clock source for each of the three channels
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* @node: list node, for tclib internal use
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*
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* On some platforms, each TC channel has its own clocks and IRQs,
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* while on others, all TC channels share the same clock and IRQ.
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* Drivers should clk_enable() all the clocks they need even though
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* all the entries in @clk may point to the same physical clock.
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* Likewise, drivers should request irqs independently for each
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* channel, but they must use IRQF_SHARED in case some of the entries
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* in @irq are actually the same IRQ.
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*/
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struct atmel_tc {
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struct platform_device *pdev;
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struct resource *iomem;
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void __iomem *regs;
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struct atmel_tcb_config *tcb_config;
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int irq[3];
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struct clk *clk[3];
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struct list_head node;
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};
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extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name);
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extern void atmel_tc_free(struct atmel_tc *tc);
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/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
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extern const u8 atmel_tc_divisors[5];
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/*
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* Two registers have block-wide controls. These are: configuring the three
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* "external" clocks (or event sources) used by the timer channels; and
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* synchronizing the timers by resetting them all at once.
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*
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* "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
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* signals. Or, it can mean "external to timer", using the TIOA output from
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* one of the other two timers that's being run in waveform mode.
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*/
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#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
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#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
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#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
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#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
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#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
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#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
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#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
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#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
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#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
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#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
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#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
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#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
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#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
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#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
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#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
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#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
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#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
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#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
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/*
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* Each TC block has three "channels", each with one counter and controls.
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*
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* Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
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* when it's not "external") is silicon-specific. AT91 platforms use one
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* set of definitions; AVR32 platforms use a different set. Don't hard-wire
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* such knowledge into your code, use the global "atmel_tc_divisors" ...
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* where index N is the divisor for clock N+1, else zero to indicate it uses
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* the 32 KiHz clock.
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*
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* The timers can be chained in various ways, and operated in "waveform"
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* generation mode (including PWM) or "capture" mode (to time events). In
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* both modes, behavior can be configured in many ways.
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*
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* Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
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* PWM output, and TIOB as either another PWM or as a trigger. Capture mode
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* uses them only as inputs.
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*/
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#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
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#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
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#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
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#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
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#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
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#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
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#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
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/* Both modes share some CMR bits */
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#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
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#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
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#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
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#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
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#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
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#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
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#define ATMEL_TC_XC0 (5 << 0)
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#define ATMEL_TC_XC1 (6 << 0)
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#define ATMEL_TC_XC2 (7 << 0)
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#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
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#define ATMEL_TC_BURST (3 << 4) /* clock gating */
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#define ATMEL_TC_GATE_NONE (0 << 4)
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#define ATMEL_TC_GATE_XC0 (1 << 4)
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#define ATMEL_TC_GATE_XC1 (2 << 4)
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#define ATMEL_TC_GATE_XC2 (3 << 4)
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#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
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/* CAPTURE mode CMR bits */
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#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
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#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
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#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
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#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
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#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
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#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
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#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
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#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
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#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
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#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
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#define ATMEL_TC_LDRA_NONE (0 << 16)
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#define ATMEL_TC_LDRA_RISING (1 << 16)
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#define ATMEL_TC_LDRA_FALLING (2 << 16)
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#define ATMEL_TC_LDRA_BOTH (3 << 16)
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#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
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#define ATMEL_TC_LDRB_NONE (0 << 18)
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#define ATMEL_TC_LDRB_RISING (1 << 18)
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#define ATMEL_TC_LDRB_FALLING (2 << 18)
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#define ATMEL_TC_LDRB_BOTH (3 << 18)
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/* WAVEFORM mode CMR bits */
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#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
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#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
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#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
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#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
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#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
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#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
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#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
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#define ATMEL_TC_EEVT (3 << 10) /* external event source */
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#define ATMEL_TC_EEVT_TIOB (0 << 10)
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#define ATMEL_TC_EEVT_XC0 (1 << 10)
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#define ATMEL_TC_EEVT_XC1 (2 << 10)
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#define ATMEL_TC_EEVT_XC2 (3 << 10)
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#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
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#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
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#define ATMEL_TC_WAVESEL_UP (0 << 13)
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#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
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#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
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#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
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#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
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#define ATMEL_TC_ACPA_NONE (0 << 16)
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#define ATMEL_TC_ACPA_SET (1 << 16)
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#define ATMEL_TC_ACPA_CLEAR (2 << 16)
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#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
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#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
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#define ATMEL_TC_ACPC_NONE (0 << 18)
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#define ATMEL_TC_ACPC_SET (1 << 18)
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#define ATMEL_TC_ACPC_CLEAR (2 << 18)
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#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
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#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
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#define ATMEL_TC_AEEVT_NONE (0 << 20)
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#define ATMEL_TC_AEEVT_SET (1 << 20)
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#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
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#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
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#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
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#define ATMEL_TC_ASWTRG_NONE (0 << 22)
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#define ATMEL_TC_ASWTRG_SET (1 << 22)
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#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
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#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
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#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
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#define ATMEL_TC_BCPB_NONE (0 << 24)
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#define ATMEL_TC_BCPB_SET (1 << 24)
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#define ATMEL_TC_BCPB_CLEAR (2 << 24)
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#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
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#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
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#define ATMEL_TC_BCPC_NONE (0 << 26)
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#define ATMEL_TC_BCPC_SET (1 << 26)
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#define ATMEL_TC_BCPC_CLEAR (2 << 26)
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#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
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#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
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#define ATMEL_TC_BEEVT_NONE (0 << 28)
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#define ATMEL_TC_BEEVT_SET (1 << 28)
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#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
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#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
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#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
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#define ATMEL_TC_BSWTRG_NONE (0 << 30)
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#define ATMEL_TC_BSWTRG_SET (1 << 30)
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#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
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#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
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#define ATMEL_TC_CV 0x10 /* counter Value */
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#define ATMEL_TC_RA 0x14 /* register A */
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#define ATMEL_TC_RB 0x18 /* register B */
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#define ATMEL_TC_RC 0x1c /* register C */
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#define ATMEL_TC_SR 0x20 /* status (read-only) */
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/* Status-only flags */
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#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
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#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
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#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
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#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
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#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
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#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
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/* Status and IRQ flags */
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#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
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#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
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#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
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#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
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#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
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#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
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#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
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#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
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#endif
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