379 lines
9.8 KiB
C
379 lines
9.8 KiB
C
/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MIPI_DSI_H
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#define MIPI_DSI_H
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#include <mach/scm-io.h>
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#include <linux/list.h>
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#ifdef BIT
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#undef BIT
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#endif
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#define BIT(x) (1<<(x))
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#define MMSS_CC_BASE_PHY 0x04000000 /* mmss clcok control */
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#define MMSS_SFPB_BASE_PHY 0x05700000 /* mmss SFPB CFG */
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#define MMSS_SERDES_BASE_PHY 0x04f01000 /* mmss (De)Serializer CFG */
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#define MIPI_DSI_BASE mipi_dsi_base
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#define MIPI_OUTP(addr, data) writel((data), (addr))
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#define MIPI_INP(addr) readl(addr)
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#ifdef CONFIG_MSM_SECURE_IO
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#define MIPI_OUTP_SECURE(addr, data) secure_writel((data), (addr))
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#define MIPI_INP_SECURE(addr) secure_readl(addr)
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#else
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#define MIPI_OUTP_SECURE(addr, data) writel((data), (addr))
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#define MIPI_INP_SECURE(addr) readl(addr)
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#endif
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#define MIPI_DSI_PRIM 1
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#define MIPI_DSI_SECD 2
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#define MIPI_DSI_PANEL_VGA 0
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#define MIPI_DSI_PANEL_WVGA 1
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#define MIPI_DSI_PANEL_WVGA_PT 2
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#define MIPI_DSI_PANEL_FWVGA_PT 3
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#define MIPI_DSI_PANEL_WSVGA_PT 4
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#define MIPI_DSI_PANEL_QHD_PT 5
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#define MIPI_DSI_PANEL_WXGA 6
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#define MIPI_DSI_PANEL_WUXGA 7
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#define MIPI_DSI_PANEL_720P_PT 8
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#define DSI_PANEL_MAX 8
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enum { /* mipi dsi panel */
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DSI_VIDEO_MODE,
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DSI_CMD_MODE,
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};
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enum {
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ST_DSI_CLK_OFF,
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ST_DSI_SUSPEND,
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ST_DSI_RESUME,
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ST_DSI_PLAYING,
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ST_DSI_NUM
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};
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enum {
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EV_DSI_UPDATE,
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EV_DSI_DONE,
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EV_DSI_TOUT,
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EV_DSI_NUM
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};
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enum {
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LANDSCAPE = 1,
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PORTRAIT = 2,
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};
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enum dsi_trigger_type {
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DSI_CMD_MODE_DMA,
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DSI_CMD_MODE_MDP,
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};
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#define DSI_NON_BURST_SYNCH_PULSE 0
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#define DSI_NON_BURST_SYNCH_EVENT 1
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#define DSI_BURST_MODE 2
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#define DSI_RGB_SWAP_RGB 0
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#define DSI_RGB_SWAP_RBG 1
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#define DSI_RGB_SWAP_BGR 2
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#define DSI_RGB_SWAP_BRG 3
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#define DSI_RGB_SWAP_GRB 4
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#define DSI_RGB_SWAP_GBR 5
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#define DSI_VIDEO_DST_FORMAT_RGB565 0
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#define DSI_VIDEO_DST_FORMAT_RGB666 1
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#define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2
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#define DSI_VIDEO_DST_FORMAT_RGB888 3
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#define DSI_CMD_DST_FORMAT_RGB111 0
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#define DSI_CMD_DST_FORMAT_RGB332 3
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#define DSI_CMD_DST_FORMAT_RGB444 4
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#define DSI_CMD_DST_FORMAT_RGB565 6
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#define DSI_CMD_DST_FORMAT_RGB666 7
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#define DSI_CMD_DST_FORMAT_RGB888 8
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#define DSI_INTR_ERROR_MASK BIT(25)
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#define DSI_INTR_ERROR BIT(24)
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#define DSI_INTR_VIDEO_DONE_MASK BIT(17)
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#define DSI_INTR_VIDEO_DONE BIT(16)
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#define DSI_INTR_CMD_MDP_DONE_MASK BIT(9)
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#define DSI_INTR_CMD_MDP_DONE BIT(8)
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#define DSI_INTR_CMD_DMA_DONE_MASK BIT(1)
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#define DSI_INTR_CMD_DMA_DONE BIT(0)
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#define DSI_MDP_TERM BIT(8)
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#define DSI_CMD_TERM BIT(0)
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#define DSI_CMD_TRIGGER_NONE 0x0 /* mdp trigger */
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#define DSI_CMD_TRIGGER_TE 0x02
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#define DSI_CMD_TRIGGER_SW 0x04
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#define DSI_CMD_TRIGGER_SW_SEOF 0x05 /* cmd dma only */
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#define DSI_CMD_TRIGGER_SW_TE 0x06
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extern struct device dsi_dev;
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extern int mipi_dsi_clk_on;
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extern u32 dsi_irq;
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extern u32 esc_byte_ratio;
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extern void __iomem *periph_base;
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extern char *mmss_cc_base; /* mutimedia sub system clock control */
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extern char *mmss_sfpb_base; /* mutimedia sub system sfpb */
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struct dsiphy_pll_divider_config {
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u32 clk_rate;
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u32 fb_divider;
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u32 ref_divider_ratio;
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u32 bit_clk_divider; /* oCLK1 */
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u32 byte_clk_divider; /* oCLK2 */
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u32 dsi_clk_divider; /* oCLK3 */
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};
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extern struct dsiphy_pll_divider_config pll_divider_config;
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struct dsi_clk_mnd_table {
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uint8 lanes;
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uint8 bpp;
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uint8 dsiclk_div;
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uint8 dsiclk_m;
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uint8 dsiclk_n;
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uint8 dsiclk_d;
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uint8 pclk_m;
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uint8 pclk_n;
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uint8 pclk_d;
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};
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static const struct dsi_clk_mnd_table mnd_table[] = {
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{ 1, 2, 8, 1, 1, 0, 1, 2, 1},
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{ 1, 3, 8, 1, 1, 0, 1, 3, 2},
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{ 2, 2, 4, 1, 1, 0, 1, 2, 1},
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{ 2, 3, 4, 1, 1, 0, 1, 3, 2},
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{ 3, 2, 1, 3, 8, 4, 3, 16, 8},
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{ 3, 3, 1, 3, 8, 4, 1, 8, 4},
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{ 4, 2, 2, 1, 1, 0, 1, 2, 1},
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{ 4, 3, 2, 1, 1, 0, 1, 3, 2},
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};
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struct dsi_clk_desc {
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uint32 src;
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uint32 m;
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uint32 n;
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uint32 d;
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uint32 mnd_mode;
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uint32 pre_div_func;
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};
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#define DSI_HOST_HDR_SIZE 4
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#define DSI_HDR_LAST BIT(31)
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#define DSI_HDR_LONG_PKT BIT(30)
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#define DSI_HDR_BTA BIT(29)
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#define DSI_HDR_VC(vc) (((vc) & 0x03) << 22)
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#define DSI_HDR_DTYPE(dtype) (((dtype) & 0x03f) << 16)
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#define DSI_HDR_DATA2(data) (((data) & 0x0ff) << 8)
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#define DSI_HDR_DATA1(data) ((data) & 0x0ff)
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#define DSI_HDR_WC(wc) ((wc) & 0x0ffff)
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#define DSI_BUF_SIZE 64
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#define MIPI_DSI_MRPS 0x04 /* Maximum Return Packet Size */
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#define MIPI_DSI_LEN 8 /* 4 x 4 - 6 - 2, bytes dcs header+crc-align */
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struct dsi_buf {
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uint32 *hdr; /* dsi host header */
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char *start; /* buffer start addr */
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char *end; /* buffer end addr */
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int size; /* size of buffer */
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char *data; /* buffer */
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int len; /* data length */
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dma_addr_t dmap; /* mapped dma addr */
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};
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/* dcs read/write */
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#define DTYPE_DCS_WRITE 0x05 /* short write, 0 parameter */
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#define DTYPE_DCS_WRITE1 0x15 /* short write, 1 parameter */
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#define DTYPE_DCS_READ 0x06 /* read */
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#define DTYPE_DCS_LWRITE 0x39 /* long write */
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/* generic read/write */
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#define DTYPE_GEN_WRITE 0x03 /* short write, 0 parameter */
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#define DTYPE_GEN_WRITE1 0x13 /* short write, 1 parameter */
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#define DTYPE_GEN_WRITE2 0x23 /* short write, 2 parameter */
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#define DTYPE_GEN_LWRITE 0x29 /* long write */
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#define DTYPE_GEN_READ 0x04 /* long read, 0 parameter */
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#define DTYPE_GEN_READ1 0x14 /* long read, 1 parameter */
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#define DTYPE_GEN_READ2 0x24 /* long read, 2 parameter */
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#define DTYPE_TEAR_ON 0x35 /* set tear on */
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#define DTYPE_MAX_PKTSIZE 0x37 /* set max packet size */
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#define DTYPE_NULL_PKT 0x09 /* null packet, no data */
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#define DTYPE_BLANK_PKT 0x19 /* blankiing packet, no data */
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#define DTYPE_CM_ON 0x02 /* color mode off */
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#define DTYPE_CM_OFF 0x12 /* color mode on */
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#define DTYPE_PERIPHERAL_OFF 0x22
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#define DTYPE_PERIPHERAL_ON 0x32
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/*
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* dcs response
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*/
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#define DTYPE_ACK_ERR_RESP 0x02
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#define DTYPE_EOT_RESP 0x08 /* end of tx */
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#define DTYPE_GEN_READ1_RESP 0x11 /* 1 parameter, short */
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#define DTYPE_GEN_READ2_RESP 0x12 /* 2 parameter, short */
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#define DTYPE_GEN_LREAD_RESP 0x1a
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#define DTYPE_DCS_LREAD_RESP 0x1c
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#define DTYPE_DCS_READ1_RESP 0x21 /* 1 parameter, short */
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#define DTYPE_DCS_READ2_RESP 0x22 /* 2 parameter, short */
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struct dsi_cmd_desc {
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int dtype;
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int last;
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int vc;
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int ack; /* ask ACK from peripheral */
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int wait;
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int dlen;
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char *payload;
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};
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typedef void (*kickoff_act)(void *);
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struct dsi_kickoff_action {
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struct list_head act_entry;
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kickoff_act action;
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void *data;
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};
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#define CMD_REQ_MAX 4
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typedef void (*fxn)(u32 data);
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#define CMD_REQ_RX 0x0001
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#define CMD_REQ_COMMIT 0x0002
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#define CMD_CLK_CTRL 0x0004
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#define CMD_REQ_NO_MAX_PKT_SIZE 0x0008
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#define CMD_MDP3_CMD_PANEL 0x80000000 /* mdp3 only */
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struct dcs_cmd_req {
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struct dsi_cmd_desc *cmds;
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int cmds_cnt;
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u32 flags;
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struct dsi_buf *rbuf;
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int rlen; /* rx length */
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fxn cb;
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};
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struct dcs_cmd_list {
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int put;
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int get;
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int tot;
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struct dcs_cmd_req list[CMD_REQ_MAX];
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};
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char *mipi_dsi_buf_reserve_hdr(struct dsi_buf *dp, int hlen);
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char *mipi_dsi_buf_init(struct dsi_buf *dp);
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void mipi_dsi_init(void);
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void mipi_dsi_lane_cfg(void);
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void mipi_dsi_bist_ctrl(void);
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int mipi_dsi_buf_alloc(struct dsi_buf *, int size);
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int mipi_dsi_cmd_dma_add(struct dsi_buf *dp, struct dsi_cmd_desc *cm);
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int mipi_dsi_cmd_reg_tx(uint32 data);
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void mipi_dsi_host_init(struct mipi_panel_info *pinfo);
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void mipi_dsi_op_mode_config(int mode);
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void mipi_dsi_cmd_mode_ctrl(int enable);
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void mdp4_dsi_cmd_trigger(void);
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void mipi_dsi_cmd_mdp_start(void);
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int mipi_dsi_ctrl_lock(int mdp);
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int mipi_dsi_ctrl_lock_query(void);
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void mipi_dsi_cmd_bta_sw_trigger(void);
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void mipi_dsi_ack_err_status(void);
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void mipi_dsi_set_tear_on(struct msm_fb_data_type *mfd);
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void mipi_dsi_set_tear_off(struct msm_fb_data_type *mfd);
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void mipi_dsi_set_backlight(struct msm_fb_data_type *mfd, int level);
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void mipi_dsi_cmd_backlight_tx(struct dsi_buf *dp);
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void mipi_dsi_pre_kickoff_action(void);
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void mipi_dsi_post_kickoff_action(void);
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void mipi_dsi_pre_kickoff_add(struct dsi_kickoff_action *act);
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void mipi_dsi_post_kickoff_add(struct dsi_kickoff_action *act);
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void mipi_dsi_pre_kickoff_del(struct dsi_kickoff_action *act);
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void mipi_dsi_post_kickoff_del(struct dsi_kickoff_action *act);
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void mipi_dsi_controller_cfg(int enable);
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void mipi_dsi_sw_reset(void);
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void mipi_dsi_mdp_busy_wait(void);
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irqreturn_t mipi_dsi_isr(int irq, void *ptr);
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void mipi_set_tx_power_mode(int mode);
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void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
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int target_type);
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int mipi_dsi_clk_div_config(uint8 bpp, uint8 lanes,
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uint32 *expected_dsi_pclk);
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int mipi_dsi_clk_init(struct platform_device *pdev);
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void mipi_dsi_clk_deinit(struct device *dev);
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#ifdef CONFIG_FB_MSM_MIPI_DSI
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void mipi_dsi_clk_enable(void);
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void mipi_dsi_clk_disable(void);
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void mipi_dsi_prepare_clocks(void);
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void mipi_dsi_unprepare_clocks(void);
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void mipi_dsi_ahb_ctrl(u32 enable);
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void mipi_dsi_phy_ctrl(int on);
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#else
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static inline void mipi_dsi_clk_enable(void)
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{
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/* empty */
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}
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void mipi_dsi_clk_disable(void)
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{
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/* empty */
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}
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void mipi_dsi_prepare_clocks(void)
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{
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/* empty */
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}
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void mipi_dsi_unprepare_clocks(void)
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{
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/* empty */
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}
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void mipi_dsi_ahb_ctrl(u32 enable)
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{
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/* empty */
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}
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void mipi_dsi_phy_ctrl(int on)
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{
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/* empty */
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}
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#endif
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void cont_splash_clk_ctrl(int enable);
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void mipi_dsi_turn_on_clks(void);
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void mipi_dsi_turn_off_clks(void);
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void mipi_dsi_clk_cfg(int on);
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int mipi_dsi_cmdlist_put(struct dcs_cmd_req *cmdreq);
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struct dcs_cmd_req *mipi_dsi_cmdlist_get(void);
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void mipi_dsi_cmdlist_commit(int from_mdp);
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void mipi_dsi_cmd_mdp_busy(void);
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#ifdef CONFIG_FB_MSM_MDP303
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void update_lane_config(struct msm_panel_info *pinfo);
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#endif
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#endif /* MIPI_DSI_H */
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