548 lines
19 KiB
C
548 lines
19 KiB
C
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MDSS_MDP_HWIO_H
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#define MDSS_MDP_HWIO_H
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#include <linux/bitops.h>
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#define IGC_LUT_ENTRIES 256
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#define GC_LUT_SEGMENTS 16
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#define ENHIST_LUT_ENTRIES 256
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#define HIST_V_SIZE 256
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#define MDSS_MDP_HW_REV_100 0x10000000
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#define MDSS_MDP_HW_REV_102 0x10020000
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#define MDSS_REG_HW_VERSION 0x0
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#define MDSS_REG_HW_INTR_STATUS 0x10
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#define MDSS_INTR_MDP BIT(0)
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#define MDSS_INTR_DSI0 BIT(4)
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#define MDSS_INTR_DSI1 BIT(5)
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#define MDSS_INTR_HDMI BIT(8)
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#define MDSS_INTR_EDP BIT(12)
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#define MDSS_MDP_REG_HW_VERSION 0x00100
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#define MDSS_MDP_REG_DISP_INTF_SEL 0x00104
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#define MDSS_MDP_REG_INTR_EN 0x00110
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#define MDSS_MDP_REG_INTR_STATUS 0x00114
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#define MDSS_MDP_REG_INTR_CLEAR 0x00118
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#define MDSS_MDP_REG_HIST_INTR_EN 0x0011C
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#define MDSS_MDP_REG_HIST_INTR_STATUS 0x00120
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#define MDSS_MDP_REG_HIST_INTR_CLEAR 0x00124
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#define MDSS_MDP_REG_SPLIT_DISPLAY_EN 0x003F4
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#define MDSS_MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x003F8
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#define MDSS_MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTRL 0x004F0
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#define MDSS_INTF_DSI 0x1
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#define MDSS_INTF_HDMI 0x3
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#define MDSS_INTF_LCDC 0x5
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#define MDSS_INTF_EDP 0x9
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#define MDSS_MDP_INTR_WB_0_DONE BIT(0)
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#define MDSS_MDP_INTR_WB_1_DONE BIT(1)
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#define MDSS_MDP_INTR_WB_2_DONE BIT(4)
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#define MDSS_MDP_INTR_PING_PONG_0_DONE BIT(8)
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#define MDSS_MDP_INTR_PING_PONG_1_DONE BIT(9)
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#define MDSS_MDP_INTR_PING_PONG_2_DONE BIT(10)
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#define MDSS_MDP_INTR_PING_PONG_0_RD_PTR BIT(12)
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#define MDSS_MDP_INTR_PING_PONG_1_RD_PTR BIT(13)
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#define MDSS_MDP_INTR_PING_PONG_2_RD_PTR BIT(14)
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#define MDSS_MDP_INTR_PING_PONG_0_WR_PTR BIT(16)
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#define MDSS_MDP_INTR_PING_PONG_1_WR_PTR BIT(17)
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#define MDSS_MDP_INTR_PING_PONG_2_WR_PTR BIT(18)
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#define MDSS_MDP_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20)
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#define MDSS_MDP_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21)
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#define MDSS_MDP_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22)
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#define MDSS_MDP_INTR_INTF_0_UNDERRUN BIT(24)
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#define MDSS_MDP_INTR_INTF_0_VSYNC BIT(25)
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#define MDSS_MDP_INTR_INTF_1_UNDERRUN BIT(26)
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#define MDSS_MDP_INTR_INTF_1_VSYNC BIT(27)
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#define MDSS_MDP_INTR_INTF_2_UNDERRUN BIT(28)
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#define MDSS_MDP_INTR_INTF_2_VSYNC BIT(29)
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#define MDSS_MDP_INTR_INTF_3_UNDERRUN BIT(30)
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#define MDSS_MDP_INTR_INTF_3_VSYNC BIT(31)
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enum mdss_mdp_intr_type {
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MDSS_MDP_IRQ_WB_ROT_COMP = 0,
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MDSS_MDP_IRQ_WB_WFD = 4,
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MDSS_MDP_IRQ_PING_PONG_COMP = 8,
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MDSS_MDP_IRQ_PING_PONG_RD_PTR = 12,
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MDSS_MDP_IRQ_PING_PONG_WR_PTR = 16,
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MDSS_MDP_IRQ_PING_PONG_AUTO_REF = 20,
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MDSS_MDP_IRQ_INTF_UNDER_RUN = 24,
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MDSS_MDP_IRQ_INTF_VSYNC = 25,
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};
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#define MDSS_MDP_REG_IGC_VIG_BASE 0x300
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#define MDSS_MDP_REG_IGC_RGB_BASE 0x310
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#define MDSS_MDP_REG_IGC_DMA_BASE 0x320
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#define MDSS_MDP_REG_IGC_DSPP_BASE 0x400
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enum mdss_mdp_ctl_index {
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MDSS_MDP_CTL0,
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MDSS_MDP_CTL1,
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MDSS_MDP_CTL2,
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MDSS_MDP_CTL3,
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MDSS_MDP_CTL4,
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MDSS_MDP_MAX_CTL
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};
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#define MDSS_MDP_REG_CTL_OFFSET(ctl) (0x00600 + ((ctl) * 0x100))
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#define MDSS_MDP_REG_CTL_LAYER(lm) ((lm) * 0x004)
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#define MDSS_MDP_REG_CTL_TOP 0x014
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#define MDSS_MDP_REG_CTL_FLUSH 0x018
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#define MDSS_MDP_REG_CTL_START 0x01C
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#define MDSS_MDP_REG_CTL_PACK_3D 0x020
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#define MDSS_MDP_CTL_OP_VIDEO_MODE (0 << 17)
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#define MDSS_MDP_CTL_OP_CMD_MODE (1 << 17)
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#define MDSS_MDP_CTL_OP_ROT0_MODE 0x1
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#define MDSS_MDP_CTL_OP_ROT1_MODE 0x2
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#define MDSS_MDP_CTL_OP_WB0_MODE 0x3
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#define MDSS_MDP_CTL_OP_WB1_MODE 0x4
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#define MDSS_MDP_CTL_OP_WFD_MODE 0x5
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#define MDSS_MDP_CTL_OP_PACK_3D_ENABLE BIT(19)
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#define MDSS_MDP_CTL_OP_PACK_3D_FRAME_INT (0 << 20)
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#define MDSS_MDP_CTL_OP_PACK_3D_H_ROW_INT (1 << 20)
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#define MDSS_MDP_CTL_OP_PACK_3D_V_ROW_INT (2 << 20)
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#define MDSS_MDP_CTL_OP_PACK_3D_COL_INT (3 << 20)
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enum mdss_mdp_sspp_index {
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MDSS_MDP_SSPP_VIG0,
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MDSS_MDP_SSPP_VIG1,
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MDSS_MDP_SSPP_VIG2,
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MDSS_MDP_SSPP_RGB0,
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MDSS_MDP_SSPP_RGB1,
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MDSS_MDP_SSPP_RGB2,
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MDSS_MDP_SSPP_DMA0,
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MDSS_MDP_SSPP_DMA1,
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MDSS_MDP_MAX_SSPP
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};
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enum mdss_mdp_sspp_fetch_type {
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MDSS_MDP_PLANE_INTERLEAVED,
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MDSS_MDP_PLANE_PLANAR,
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MDSS_MDP_PLANE_PSEUDO_PLANAR,
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};
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enum mdss_mdp_sspp_chroma_samp_type {
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MDSS_MDP_CHROMA_RGB,
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MDSS_MDP_CHROMA_H2V1,
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MDSS_MDP_CHROMA_H1V2,
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MDSS_MDP_CHROMA_420
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};
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#define MDSS_MDP_REG_SSPP_OFFSET(pipe) (0x01200 + ((pipe) * 0x400))
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#define MDSS_MDP_REG_SSPP_SRC_SIZE 0x000
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#define MDSS_MDP_REG_SSPP_SRC_IMG_SIZE 0x004
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#define MDSS_MDP_REG_SSPP_SRC_XY 0x008
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#define MDSS_MDP_REG_SSPP_OUT_SIZE 0x00C
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#define MDSS_MDP_REG_SSPP_OUT_XY 0x010
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#define MDSS_MDP_REG_SSPP_SRC0_ADDR 0x014
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#define MDSS_MDP_REG_SSPP_SRC1_ADDR 0x018
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#define MDSS_MDP_REG_SSPP_SRC2_ADDR 0x01C
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#define MDSS_MDP_REG_SSPP_SRC3_ADDR 0x020
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#define MDSS_MDP_REG_SSPP_SRC_YSTRIDE0 0x024
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#define MDSS_MDP_REG_SSPP_SRC_YSTRIDE1 0x028
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#define MDSS_MDP_REG_SSPP_STILE_FRAME_SIZE 0x02C
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#define MDSS_MDP_REG_SSPP_SRC_FORMAT 0x030
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#define MDSS_MDP_REG_SSPP_SRC_UNPACK_PATTERN 0x034
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#define MDSS_MDP_REG_SSPP_REQPRIO_FIFO_WM_0 0x050
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#define MDSS_MDP_REG_SSPP_REQPRIO_FIFO_WM_1 0x054
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#define MDSS_MDP_REG_SSPP_REQPRIO_FIFO_WM_2 0x058
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#define MDSS_MDP_REG_SSPP_SRC_OP_MODE 0x038
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#define MDSS_MDP_OP_DEINTERLACE BIT(22)
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#define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23)
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#define MDSS_MDP_OP_IGC_ROM_1 BIT(18)
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#define MDSS_MDP_OP_IGC_ROM_0 BIT(17)
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#define MDSS_MDP_OP_IGC_EN BIT(16)
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#define MDSS_MDP_OP_FLIP_UD BIT(14)
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#define MDSS_MDP_OP_FLIP_LR BIT(13)
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#define MDSS_MDP_OP_BWC_EN BIT(0)
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#define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1)
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#define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1)
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#define MDSS_MDP_OP_BWC_Q_MED (2 << 1)
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#define MDSS_MDP_REG_SSPP_SRC_CONSTANT_COLOR 0x03C
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#define MDSS_MDP_REG_SSPP_FETCH_CONFIG 0x048
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#define MDSS_MDP_REG_SSPP_VC1_RANGE 0x04C
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#define MDSS_MDP_REG_SSPP_SRC_ADDR_SW_STATUS 0x070
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#define MDSS_MDP_REG_SSPP_CURRENT_SRC0_ADDR 0x0A4
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#define MDSS_MDP_REG_SSPP_CURRENT_SRC1_ADDR 0x0A8
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#define MDSS_MDP_REG_SSPP_CURRENT_SRC2_ADDR 0x0AC
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#define MDSS_MDP_REG_SSPP_CURRENT_SRC3_ADDR 0x0B0
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#define MDSS_MDP_REG_SSPP_DECIMATION_CONFIG 0x0B4
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#define MDSS_MDP_REG_VIG_OP_MODE 0x200
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#define MDSS_MDP_REG_VIG_QSEED2_CONFIG 0x204
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#define MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPX 0x210
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#define MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPY 0x214
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#define MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPX 0x218
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#define MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPY 0x21C
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#define MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEX 0x220
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#define MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEY 0x224
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#define MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEX 0x228
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#define MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEY 0x22C
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#define MDSS_MDP_REG_VIG_QSEED2_SHARP 0x230
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#define MDSS_MDP_REG_VIG_PA_BASE 0x310
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#define MDSS_MDP_REG_SCALE_CONFIG 0x204
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#define MDSS_MDP_REG_SCALE_PHASE_STEP_X 0x210
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#define MDSS_MDP_REG_SCALE_PHASE_STEP_Y 0x214
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#define MDSS_MDP_REG_SCALE_INIT_PHASE_X 0x220
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#define MDSS_MDP_REG_SCALE_INIT_PHASE_Y 0x224
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#define MDSS_MDP_REG_VIG_CSC_0_BASE 0x280
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#define MDSS_MDP_REG_VIG_CSC_1_BASE 0x320
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#define MDSS_MDP_REG_VIG_HIST_CTL_BASE 0x2C4
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#define MDSS_MDP_REG_VIG_HIST_LUT_BASE 0x2F0
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#define MDSS_MDP_SCALE_FILTER_NEAREST 0x0
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#define MDSS_MDP_SCALE_FILTER_BIL 0x1
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#define MDSS_MDP_SCALE_FILTER_PCMN 0x2
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#define MDSS_MDP_SCALE_FILTER_CA 0x3
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#define MDSS_MDP_SCALEY_EN BIT(1)
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#define MDSS_MDP_SCALEX_EN BIT(0)
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#define MDSS_MDP_FMT_SOLID_FILL 0x4037FF
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#define MDSS_MDP_NUM_REG_MIXERS 3
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#define MDSS_MDP_NUM_WB_MIXERS 2
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enum mdss_mdp_mixer_intf_index {
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MDSS_MDP_INTF_LAYERMIXER0,
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MDSS_MDP_INTF_LAYERMIXER1,
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MDSS_MDP_INTF_LAYERMIXER2,
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MDSS_MDP_INTF_MAX_LAYERMIXER,
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};
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enum mdss_mdp_mixer_wb_index {
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MDSS_MDP_WB_LAYERMIXER0,
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MDSS_MDP_WB_LAYERMIXER1,
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MDSS_MDP_WB_MAX_LAYERMIXER,
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};
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enum mdss_mdp_stage_index {
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MDSS_MDP_STAGE_UNUSED,
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MDSS_MDP_STAGE_BASE,
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MDSS_MDP_STAGE_0,
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MDSS_MDP_STAGE_1,
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MDSS_MDP_STAGE_2,
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MDSS_MDP_STAGE_3,
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MDSS_MDP_MAX_STAGE
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};
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enum mdss_mdp_blend_index {
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MDSS_MDP_BLEND_STAGE0,
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MDSS_MDP_BLEND_STAGE1,
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MDSS_MDP_BLEND_STAGE2,
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MDSS_MDP_BLEND_STAGE3,
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MDSS_MDP_MAX_BLEND_STAGE,
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};
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#define MDSS_MDP_REG_LM_OFFSET(lm) (0x03200 + ((lm) * 0x400))
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#define MDSS_MDP_REG_LM_OP_MODE 0x000
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#define MDSS_MDP_REG_LM_OUT_SIZE 0x004
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#define MDSS_MDP_REG_LM_BORDER_COLOR_0 0x008
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#define MDSS_MDP_REG_LM_BORDER_COLOR_1 0x010
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#define MDSS_MDP_REG_LM_BLEND_OFFSET(stage) (0x20 + ((stage) * 0x30))
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#define MDSS_MDP_REG_LM_BLEND_OP 0x00
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#define MDSS_MDP_REG_LM_BLEND_FG_ALPHA 0x04
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#define MDSS_MDP_REG_LM_BLEND_BG_ALPHA 0x08
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#define MDSS_MDP_REG_LM_BLEND_FG_TRANSP_LOW0 0x0C
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#define MDSS_MDP_REG_LM_BLEND_FG_TRANSP_LOW1 0x10
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#define MDSS_MDP_REG_LM_BLEND_FG_TRANSP_HIGH0 0x14
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#define MDSS_MDP_REG_LM_BLEND_FG_TRANSP_HIGH1 0x18
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#define MDSS_MDP_REG_LM_BLEND_BG_TRANSP_LOW0 0x1C
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#define MDSS_MDP_REG_LM_BLEND_BG_TRANSP_LOW1 0x20
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#define MDSS_MDP_REG_LM_BLEND_BG_TRANSP_HIGH0 0x24
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#define MDSS_MDP_REG_LM_BLEND_BG_TRANSP_HIGH1 0x28
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#define MDSS_MDP_REG_LM_CURSOR_IMG_SIZE 0xE0
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#define MDSS_MDP_REG_LM_CURSOR_SIZE 0xE4
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#define MDSS_MDP_REG_LM_CURSOR_XY 0xE8
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#define MDSS_MDP_REG_LM_CURSOR_STRIDE 0xDC
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#define MDSS_MDP_REG_LM_CURSOR_FORMAT 0xEC
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#define MDSS_MDP_REG_LM_CURSOR_BASE_ADDR 0xF0
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#define MDSS_MDP_REG_LM_CURSOR_START_XY 0xF4
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#define MDSS_MDP_REG_LM_CURSOR_BLEND_CONFIG 0xF8
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#define MDSS_MDP_REG_LM_CURSOR_BLEND_PARAM 0xFC
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#define MDSS_MDP_REG_LM_CURSOR_BLEND_TRANSP_LOW0 0x100
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#define MDSS_MDP_REG_LM_CURSOR_BLEND_TRANSP_LOW1 0x104
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#define MDSS_MDP_REG_LM_CURSOR_BLEND_TRANSP_HIGH0 0x108
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#define MDSS_MDP_REG_LM_CURSOR_BLEND_TRANSP_HIGH1 0x10C
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#define MDSS_MDP_REG_LM_GC_LUT_BASE 0x110
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#define MDSS_MDP_LM_BORDER_COLOR (1 << 24)
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#define MDSS_MDP_LM_CURSOR_OUT (1 << 25)
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#define MDSS_MDP_BLEND_FG_ALPHA_FG_CONST (0 << 0)
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#define MDSS_MDP_BLEND_FG_ALPHA_BG_CONST (1 << 0)
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#define MDSS_MDP_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)
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#define MDSS_MDP_BLEND_FG_ALPHA_BG_PIXEL (3 << 0)
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#define MDSS_MDP_BLEND_FG_INV_ALPHA (1 << 2)
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#define MDSS_MDP_BLEND_FG_MOD_ALPHA (1 << 3)
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#define MDSS_MDP_BLEND_FG_INV_MOD_ALPHA (1 << 4)
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#define MDSS_MDP_BLEND_FG_TRANSP_EN (1 << 5)
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#define MDSS_MDP_BLEND_BG_ALPHA_FG_CONST (0 << 8)
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#define MDSS_MDP_BLEND_BG_ALPHA_BG_CONST (1 << 8)
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#define MDSS_MDP_BLEND_BG_ALPHA_FG_PIXEL (2 << 8)
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#define MDSS_MDP_BLEND_BG_ALPHA_BG_PIXEL (3 << 8)
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#define MDSS_MDP_BLEND_BG_INV_ALPHA (1 << 10)
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#define MDSS_MDP_BLEND_BG_MOD_ALPHA (1 << 11)
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#define MDSS_MDP_BLEND_BG_INV_MOD_ALPHA (1 << 12)
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#define MDSS_MDP_BLEND_BG_TRANSP_EN (1 << 13)
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enum mdss_mdp_writeback_index {
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MDSS_MDP_WRITEBACK0,
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MDSS_MDP_WRITEBACK1,
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MDSS_MDP_WRITEBACK2,
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MDSS_MDP_WRITEBACK3,
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MDSS_MDP_WRITEBACK4,
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MDSS_MDP_MAX_WRITEBACK
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};
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#define MDSS_MDP_REG_WB_OFFSET(wb) (0x11100 + ((wb) * 0x2000))
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#define MDSS_MDP_REG_WB_DST_FORMAT 0x000
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#define MDSS_MDP_REG_WB_DST_OP_MODE 0x004
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#define MDSS_MDP_REG_WB_DST_PACK_PATTERN 0x008
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#define MDSS_MDP_REG_WB_DST0_ADDR 0x00C
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#define MDSS_MDP_REG_WB_DST1_ADDR 0x010
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#define MDSS_MDP_REG_WB_DST2_ADDR 0x014
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#define MDSS_MDP_REG_WB_DST3_ADDR 0x018
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#define MDSS_MDP_REG_WB_DST_YSTRIDE0 0x01C
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#define MDSS_MDP_REG_WB_DST_YSTRIDE1 0x020
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#define MDSS_MDP_REG_WB_DST_YSTRIDE1 0x020
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#define MDSS_MDP_REG_WB_DST_DITHER_BITDEPTH 0x024
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#define MDSS_MDP_REG_WB_DST_MATRIX_ROW0 0x030
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#define MDSS_MDP_REG_WB_DST_MATRIX_ROW1 0x034
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#define MDSS_MDP_REG_WB_DST_MATRIX_ROW2 0x038
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#define MDSS_MDP_REG_WB_DST_MATRIX_ROW3 0x03C
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#define MDSS_MDP_REG_WB_ROTATION_DNSCALER 0x050
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#define MDSS_MDP_REG_WB_N16_INIT_PHASE_X_C03 0x060
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#define MDSS_MDP_REG_WB_N16_INIT_PHASE_X_C12 0x064
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#define MDSS_MDP_REG_WB_N16_INIT_PHASE_Y_C03 0x068
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#define MDSS_MDP_REG_WB_N16_INIT_PHASE_Y_C12 0x06C
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#define MDSS_MDP_REG_WB_OUT_SIZE 0x074
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#define MDSS_MDP_REG_WB_ALPHA_X_VALUE 0x078
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#define MDSS_MDP_REG_WB_CSC_BASE 0x260
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#define MDSS_MDP_REG_WB_DST_ADDR_SW_STATUS 0x2B0
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#define MDSS_MDP_REG_AD_BYPASS 0x000
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#define MDSS_MDP_REG_AD_CTRL_0 0x004
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#define MDSS_MDP_REG_AD_CTRL_1 0x008
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#define MDSS_MDP_REG_AD_FRAME_SIZE 0x00C
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#define MDSS_MDP_REG_AD_CON_CTRL_0 0x010
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#define MDSS_MDP_REG_AD_CON_CTRL_1 0x014
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#define MDSS_MDP_REG_AD_STR_MAN 0x018
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#define MDSS_MDP_REG_AD_VAR 0x01C
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#define MDSS_MDP_REG_AD_DITH 0x020
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#define MDSS_MDP_REG_AD_DITH_CTRL 0x024
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#define MDSS_MDP_REG_AD_AMP_LIM 0x028
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#define MDSS_MDP_REG_AD_SLOPE 0x02C
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#define MDSS_MDP_REG_AD_BW_LVL 0x030
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#define MDSS_MDP_REG_AD_LOGO_POS 0x034
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#define MDSS_MDP_REG_AD_LUT_FI 0x038
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#define MDSS_MDP_REG_AD_LUT_CC 0x07C
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#define MDSS_MDP_REG_AD_STR_LIM 0x0C8
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#define MDSS_MDP_REG_AD_CALIB_AB 0x0CC
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#define MDSS_MDP_REG_AD_CALIB_CD 0x0D0
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#define MDSS_MDP_REG_AD_MODE_SEL 0x0D4
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#define MDSS_MDP_REG_AD_TFILT_CTRL 0x0D8
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#define MDSS_MDP_REG_AD_BL_MINMAX 0x0DC
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#define MDSS_MDP_REG_AD_BL 0x0E0
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#define MDSS_MDP_REG_AD_BL_MAX 0x0E8
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#define MDSS_MDP_REG_AD_AL 0x0EC
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#define MDSS_MDP_REG_AD_AL_MIN 0x0F0
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#define MDSS_MDP_REG_AD_AL_FILT 0x0F4
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#define MDSS_MDP_REG_AD_CFG_BUF 0x0F8
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#define MDSS_MDP_REG_AD_LUT_AL 0x100
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#define MDSS_MDP_REG_AD_TARG_STR 0x144
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#define MDSS_MDP_REG_AD_START_CALC 0x148
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#define MDSS_MDP_REG_AD_STR_OUT 0x14C
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#define MDSS_MDP_REG_AD_BL_OUT 0x154
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#define MDSS_MDP_REG_AD_CALC_DONE 0x158
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enum mdss_mdp_dspp_index {
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MDSS_MDP_DSPP0,
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MDSS_MDP_DSPP1,
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MDSS_MDP_DSPP2,
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MDSS_MDP_MAX_DSPP
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};
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#define MDSS_MDP_REG_DSPP_OFFSET(pipe) (0x4600 + ((pipe) * 0x400))
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#define MDSS_MDP_REG_DSPP_OP_MODE 0x000
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#define MDSS_MDP_REG_DSPP_PCC_BASE 0x030
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#define MDSS_MDP_REG_DSPP_DITHER_DEPTH 0x150
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#define MDSS_MDP_REG_DSPP_HIST_CTL_BASE 0x210
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#define MDSS_MDP_REG_DSPP_HIST_LUT_BASE 0x230
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#define MDSS_MDP_REG_DSPP_PA_BASE 0x238
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#define MDSS_MDP_REG_DSPP_GAMUT_BASE 0x2DC
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#define MDSS_MDP_REG_DSPP_GC_BASE 0x2B0
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enum mdss_mpd_intf_index {
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MDSS_MDP_NO_INTF,
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MDSS_MDP_INTF0,
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MDSS_MDP_INTF1,
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MDSS_MDP_INTF2,
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MDSS_MDP_INTF3,
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MDSS_MDP_MAX_INTF
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};
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#define MDSS_MDP_REG_INTF_OFFSET(intf) (0x20F00 + ((intf) * 0x200))
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#define MDSS_MDP_REG_INTF_TIMING_ENGINE_EN 0x000
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#define MDSS_MDP_REG_INTF_CONFIG 0x004
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#define MDSS_MDP_REG_INTF_HSYNC_CTL 0x008
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#define MDSS_MDP_REG_INTF_VSYNC_PERIOD_F0 0x00C
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#define MDSS_MDP_REG_INTF_VSYNC_PERIOD_F1 0x010
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#define MDSS_MDP_REG_INTF_VSYNC_PULSE_WIDTH_F0 0x014
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#define MDSS_MDP_REG_INTF_VSYNC_PULSE_WIDTH_F1 0x018
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#define MDSS_MDP_REG_INTF_DISPLAY_V_START_F0 0x01C
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#define MDSS_MDP_REG_INTF_DISPLAY_V_START_F1 0x020
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#define MDSS_MDP_REG_INTF_DISPLAY_V_END_F0 0x024
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#define MDSS_MDP_REG_INTF_DISPLAY_V_END_F1 0x028
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#define MDSS_MDP_REG_INTF_ACTIVE_V_START_F0 0x02C
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#define MDSS_MDP_REG_INTF_ACTIVE_V_START_F1 0x030
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#define MDSS_MDP_REG_INTF_ACTIVE_V_END_F0 0x034
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#define MDSS_MDP_REG_INTF_ACTIVE_V_END_F1 0x038
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#define MDSS_MDP_REG_INTF_DISPLAY_HCTL 0x03C
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#define MDSS_MDP_REG_INTF_ACTIVE_HCTL 0x040
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#define MDSS_MDP_REG_INTF_BORDER_COLOR 0x044
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#define MDSS_MDP_REG_INTF_UNDERFLOW_COLOR 0x048
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#define MDSS_MDP_REG_INTF_HSYNC_SKEW 0x04C
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#define MDSS_MDP_REG_INTF_POLARITY_CTL 0x050
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#define MDSS_MDP_REG_INTF_TEST_CTL 0x054
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#define MDSS_MDP_REG_INTF_TP_COLOR0 0x058
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#define MDSS_MDP_REG_INTF_TP_COLOR1 0x05C
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#define MDSS_MDP_REG_INTF_FRAME_LINE_COUNT_EN 0x0A8
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#define MDSS_MDP_REG_INTF_FRAME_COUNT 0x0AC
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#define MDSS_MDP_REG_INTF_LINE_COUNT 0x0B0
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#define MDSS_MDP_REG_INTF_DEFLICKER_CONFIG 0x0F0
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#define MDSS_MDP_REG_INTF_DEFLICKER_STRNG_COEFF 0x0F4
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#define MDSS_MDP_REG_INTF_DEFLICKER_WEAK_COEFF 0x0F8
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#define MDSS_MDP_REG_INTF_DSI_CMD_MODE_TRIGGER_EN 0x084
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#define MDSS_MDP_REG_INTF_PANEL_FORMAT 0x090
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#define MDSS_MDP_REG_INTF_TPG_ENABLE 0x100
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#define MDSS_MDP_REG_INTF_TPG_MAIN_CONTROL 0x104
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#define MDSS_MDP_REG_INTF_TPG_VIDEO_CONFIG 0x108
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#define MDSS_MDP_REG_INTF_TPG_COMPONENT_LIMITS 0x10C
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#define MDSS_MDP_REG_INTF_TPG_RECTANGLE 0x110
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#define MDSS_MDP_REG_INTF_TPG_INITIAL_VALUE 0x114
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#define MDSS_MDP_REG_INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118
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#define MDSS_MDP_REG_INTF_TPG_RGB_MAPPING 0x11C
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#define MDSS_MDP_REG_INTF_FRAME_LINE_COUNT_EN 0x0A8
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#define MDSS_MDP_REG_INTF_FRAME_COUNT 0x0AC
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#define MDSS_MDP_REG_INTF_LINE_COUNT 0x0B0
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#define MDSS_MDP_PANEL_FORMAT_RGB888 0x213F
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#define MDSS_MDP_PANEL_FORMAT_RGB666 0x212A
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enum mdss_mdp_pingpong_index {
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MDSS_MDP_PINGPONG0,
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MDSS_MDP_PINGPONG1,
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MDSS_MDP_PINGPONG2,
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MDSS_MDP_MAX_PINGPONG
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};
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#define MDSS_MDP_REG_PP_TEAR_CHECK_EN 0x000
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#define MDSS_MDP_REG_PP_SYNC_CONFIG_VSYNC 0x004
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#define MDSS_MDP_REG_PP_SYNC_CONFIG_HEIGHT 0x008
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#define MDSS_MDP_REG_PP_SYNC_WRCOUNT 0x00C
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#define MDSS_MDP_REG_PP_VSYNC_INIT_VAL 0x010
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#define MDSS_MDP_REG_PP_INT_COUNT_VAL 0x014
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#define MDSS_MDP_REG_PP_SYNC_THRESH 0x018
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#define MDSS_MDP_REG_PP_START_POS 0x01C
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#define MDSS_MDP_REG_PP_RD_PTR_IRQ 0x020
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#define MDSS_MDP_REG_PP_WR_PTR_IRQ 0x024
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#define MDSS_MDP_REG_PP_OUT_LINE_COUNT 0x028
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#define MDSS_MDP_REG_PP_LINE_COUNT 0x02C
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#define MDSS_MDP_REG_PP_AUTOREFRESH_CONFIG 0x030
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#define MDSS_MDP_REG_PP_FBC_MODE 0x034
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#define MDSS_MDP_REG_PP_FBC_BUDGET_CTL 0x038
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#define MDSS_MDP_REG_PP_FBC_LOSSY_MODE 0x03C
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#define MDSS_MDP_REG_SMP_ALLOC_W0 0x00180
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#define MDSS_MDP_REG_SMP_ALLOC_R0 0x00230
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#define MDSS_MDP_SMP_MMB_BLOCKS 22
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enum mdss_mdp_smp_client_index {
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MDSS_MDP_SMP_CLIENT_UNUSED,
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MDSS_MDP_SMP_CLIENT_VIG0_FETCH_Y,
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MDSS_MDP_SMP_CLIENT_VIG0_FETCH_CR,
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MDSS_MDP_SMP_CLIENT_VIG0_FETCH_CB,
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MDSS_MDP_SMP_CLIENT_VIG1_FETCH_Y,
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MDSS_MDP_SMP_CLIENT_VIG1_FETCH_CR,
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MDSS_MDP_SMP_CLIENT_VIG1_FETCH_CB,
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MDSS_MDP_SMP_CLIENT_VIG2_FETCH_Y,
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MDSS_MDP_SMP_CLIENT_VIG2_FETCH_CR,
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MDSS_MDP_SMP_CLIENT_VIG2_FETCH_CB,
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MDSS_MDP_SMP_CLIENT_DMA0_FETCH_Y,
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MDSS_MDP_SMP_CLIENT_DMA0_FETCH_CR,
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MDSS_MDP_SMP_CLIENT_DMA0_FETCH_CB,
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MDSS_MDP_SMP_CLIENT_DMA1_FETCH_Y,
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MDSS_MDP_SMP_CLIENT_DMA1_FETCH_CR,
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MDSS_MDP_SMP_CLIENT_DMA1_FETCH_CB,
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MDSS_MDP_SMP_CLIENT_RGB0_FETCH,
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MDSS_MDP_SMP_CLIENT_RGB1_FETCH,
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MDSS_MDP_SMP_CLIENT_RGB2_FETCH,
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};
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#define MDSS_MDP_LP_MISR_SEL 0x450
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#define MDSS_MDP_LP_MISR_CTRL_MDP 0x454
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#define MDSS_MDP_LP_MISR_CTRL_HDMI 0x458
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#define MDSS_MDP_LP_MISR_CTRL_EDP 0x45C
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#define MDSS_MDP_LP_MISR_CTRL_DSI0 0x460
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#define MDSS_MDP_LP_MISR_CTRL_DSI1 0x464
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#define MDSS_MDP_LP_MISR_SIGN_MDP 0x468
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#define MDSS_MDP_LP_MISR_SIGN_EDP 0x46C
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#define MDSS_MDP_LP_MISR_SIGN_HDMI 0x470
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#define MDSS_MDP_LP_MISR_SIGN_DSI0 0x474
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#define MDSS_MDP_LP_MISR_SIGN_DSI1 0x478
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#define MDSS_MDP_LP_MISR_CTRL_FRAME_COUNT_MASK 0xFF
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#define MDSS_MDP_LP_MISR_CTRL_ENABLE BIT(8)
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#define MDSS_MDP_LP_MISR_CTRL_STATUS BIT(9)
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#define MDSS_MDP_LP_MISR_CTRL_STATUS_CLEAR BIT(10)
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#define MDSS_MDP_LP_MISR_SEL_LMIX0_BLEND 0x08
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#define MDSS_MDP_LP_MISR_SEL_LMIX0_GC 0x09
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#define MDSS_MDP_LP_MISR_SEL_LMIX1_BLEND 0x0A
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#define MDSS_MDP_LP_MISR_SEL_LMIX1_GC 0x0B
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#define MDSS_MDP_LP_MISR_SEL_LMIX2_BLEND 0x0C
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#define MDSS_MDP_LP_MISR_SEL_LMIX2_GC 0x0D
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#define MDSS_MDP_LP_MISR_SEL_LMIX3_BLEND 0x0E
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#define MDSS_MDP_LP_MISR_SEL_LMIX3_GC 0x0F
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#define MDSS_MDP_LP_MISR_SEL_LMIX4_BLEND 0x10
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#define MDSS_MDP_LP_MISR_SEL_LMIX4_GC 0x11
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#endif
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