95 lines
2.8 KiB
C
95 lines
2.8 KiB
C
/*
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* Copyright (C) 2010 Google, Inc.
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* Author: Dima Zavin <dima@android.com>
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*
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* Based on code from Code Aurora Forum.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "mdp_hw.h"
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static void mdp_dma_to_mddi(void *priv, uint32_t addr, uint32_t stride,
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uint32_t width, uint32_t height, uint32_t x,
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uint32_t y)
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{
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struct mdp_info *mdp = priv;
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uint32_t dma2_cfg;
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uint16_t ld_param = 0; /* 0=PRIM, 1=SECD, 2=EXT */
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dma2_cfg = DMA_PACK_TIGHT |
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DMA_PACK_ALIGN_LSB;
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dma2_cfg |= mdp->dma_format;
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dma2_cfg |= mdp->dma_pack_pattern;
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dma2_cfg |= DMA_DITHER_EN;
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/* 666 18BPP */
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dma2_cfg |= DMA_DSTC0G_6BITS | DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
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/* setup size, address, and stride */
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mdp_writel(mdp, (height << 16) | (width), MDP_DMA_P_SIZE);
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mdp_writel(mdp, addr, MDP_DMA_P_IBUF_ADDR);
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mdp_writel(mdp, stride, MDP_DMA_P_IBUF_Y_STRIDE);
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/* set y & x offset and MDDI transaction parameters */
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mdp_writel(mdp, (y << 16) | (x), MDP_DMA_P_OUT_XY);
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mdp_writel(mdp, ld_param, MDP_MDDI_PARAM_WR_SEL);
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mdp_writel(mdp, (MDDI_VDO_PACKET_DESC << 16) | MDDI_VDO_PACKET_PRIM,
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MDP_MDDI_PARAM);
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mdp_writel(mdp, 0x1, MDP_MDDI_DATA_XFR);
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mdp_writel(mdp, dma2_cfg, MDP_DMA_P_CONFIG);
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mdp_writel(mdp, 0, MDP_DMA_P_START);
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}
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int mdp_hw_init(struct mdp_info *mdp)
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{
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int ret;
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ret = mdp_out_if_register(&mdp->mdp_dev, MSM_MDDI_PMDH_INTERFACE, mdp,
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MDP_DMA_P_DONE, mdp_dma_to_mddi);
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if (ret)
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return ret;
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mdp_writel(mdp, 0, MDP_INTR_ENABLE);
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mdp_writel(mdp, 0, MDP_DMA_P_HIST_INTR_ENABLE);
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/* XXX: why set this? QCT says it should be > mdp_pclk,
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* but they never set the clkrate of pclk */
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clk_set_rate(mdp->clk, 122880000); /* 122.88 Mhz */
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pr_info("%s: mdp_clk=%lu\n", __func__, clk_get_rate(mdp->clk));
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/* TODO: Configure the VG/RGB pipes fetch data */
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/* this should work for any mdp_clk freq.
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* TODO: use different value for mdp_clk freqs >= 90Mhz */
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mdp_writel(mdp, 0x27, MDP_DMA_P_FETCH_CFG); /* 8 bytes-burst x 8 req */
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mdp_writel(mdp, 0x3, MDP_EBI2_PORTMAP_MODE);
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/* 3 pending requests */
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mdp_writel(mdp, 0x02222, MDP_MAX_RD_PENDING_CMD_CONFIG);
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/* no overlay processing, sw controls everything */
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mdp_writel(mdp, 0, MDP_LAYERMIXER_IN_CFG);
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mdp_writel(mdp, 1 << 3, MDP_OVERLAYPROC0_CFG);
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mdp_writel(mdp, 1 << 3, MDP_OVERLAYPROC1_CFG);
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/* XXX: HACK! hardcode to do mddi on primary */
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mdp_writel(mdp, 0x2, MDP_DISP_INTF_SEL);
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return 0;
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}
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