371 lines
8.9 KiB
C
371 lines
8.9 KiB
C
/*
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* Generic Broadcom Home Networking Division (HND) DMA engine HW interface
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* This supports the following chips: BCM42xx, 44xx, 47xx .
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*
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* Copyright (C) 1999-2012, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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* $Id: sbhnddma.h 309193 2012-01-19 00:03:57Z $
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*/
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#ifndef _sbhnddma_h_
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#define _sbhnddma_h_
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typedef volatile struct {
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uint32 control;
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uint32 addr;
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uint32 ptr;
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uint32 status;
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} dma32regs_t;
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typedef volatile struct {
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dma32regs_t xmt;
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dma32regs_t rcv;
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} dma32regp_t;
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typedef volatile struct {
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uint32 fifoaddr;
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uint32 fifodatalow;
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uint32 fifodatahigh;
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uint32 pad;
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} dma32diag_t;
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typedef volatile struct {
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uint32 ctrl;
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uint32 addr;
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} dma32dd_t;
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#define D32RINGALIGN_BITS 12
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#define D32MAXRINGSZ (1 << D32RINGALIGN_BITS)
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#define D32RINGALIGN (1 << D32RINGALIGN_BITS)
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#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
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#define XC_XE ((uint32)1 << 0)
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#define XC_SE ((uint32)1 << 1)
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#define XC_LE ((uint32)1 << 2)
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#define XC_FL ((uint32)1 << 4)
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#define XC_MR_MASK 0x000000C0
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#define XC_MR_SHIFT 6
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#define XC_PD ((uint32)1 << 11)
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#define XC_AE ((uint32)3 << 16)
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#define XC_AE_SHIFT 16
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#define XC_BL_MASK 0x001C0000
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#define XC_BL_SHIFT 18
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#define XC_PC_MASK 0x00E00000
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#define XC_PC_SHIFT 21
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#define XC_PT_MASK 0x03000000
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#define XC_PT_SHIFT 24
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#define DMA_MR_1 0
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#define DMA_MR_2 1
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#define DMA_BL_16 0
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#define DMA_BL_32 1
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#define DMA_BL_64 2
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#define DMA_BL_128 3
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#define DMA_BL_256 4
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#define DMA_BL_512 5
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#define DMA_BL_1024 6
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#define DMA_PC_0 0
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#define DMA_PC_4 1
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#define DMA_PC_8 2
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#define DMA_PC_16 3
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#define DMA_PT_1 0
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#define DMA_PT_2 1
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#define DMA_PT_4 2
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#define DMA_PT_8 3
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#define XP_LD_MASK 0xfff
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#define XS_CD_MASK 0x0fff
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#define XS_XS_MASK 0xf000
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#define XS_XS_SHIFT 12
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#define XS_XS_DISABLED 0x0000
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#define XS_XS_ACTIVE 0x1000
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#define XS_XS_IDLE 0x2000
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#define XS_XS_STOPPED 0x3000
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#define XS_XS_SUSP 0x4000
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#define XS_XE_MASK 0xf0000
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#define XS_XE_SHIFT 16
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#define XS_XE_NOERR 0x00000
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#define XS_XE_DPE 0x10000
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#define XS_XE_DFU 0x20000
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#define XS_XE_BEBR 0x30000
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#define XS_XE_BEDA 0x40000
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#define XS_AD_MASK 0xfff00000
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#define XS_AD_SHIFT 20
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#define RC_RE ((uint32)1 << 0)
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#define RC_RO_MASK 0xfe
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#define RC_RO_SHIFT 1
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#define RC_FM ((uint32)1 << 8)
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#define RC_SH ((uint32)1 << 9)
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#define RC_OC ((uint32)1 << 10)
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#define RC_PD ((uint32)1 << 11)
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#define RC_AE ((uint32)3 << 16)
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#define RC_AE_SHIFT 16
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#define RC_BL_MASK 0x001C0000
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#define RC_BL_SHIFT 18
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#define RC_PC_MASK 0x00E00000
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#define RC_PC_SHIFT 21
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#define RC_PT_MASK 0x03000000
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#define RC_PT_SHIFT 24
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#define RP_LD_MASK 0xfff
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#define RS_CD_MASK 0x0fff
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#define RS_RS_MASK 0xf000
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#define RS_RS_SHIFT 12
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#define RS_RS_DISABLED 0x0000
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#define RS_RS_ACTIVE 0x1000
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#define RS_RS_IDLE 0x2000
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#define RS_RS_STOPPED 0x3000
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#define RS_RE_MASK 0xf0000
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#define RS_RE_SHIFT 16
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#define RS_RE_NOERR 0x00000
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#define RS_RE_DPE 0x10000
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#define RS_RE_DFO 0x20000
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#define RS_RE_BEBW 0x30000
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#define RS_RE_BEDA 0x40000
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#define RS_AD_MASK 0xfff00000
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#define RS_AD_SHIFT 20
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#define FA_OFF_MASK 0xffff
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#define FA_SEL_MASK 0xf0000
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#define FA_SEL_SHIFT 16
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#define FA_SEL_XDD 0x00000
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#define FA_SEL_XDP 0x10000
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#define FA_SEL_RDD 0x40000
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#define FA_SEL_RDP 0x50000
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#define FA_SEL_XFD 0x80000
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#define FA_SEL_XFP 0x90000
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#define FA_SEL_RFD 0xc0000
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#define FA_SEL_RFP 0xd0000
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#define FA_SEL_RSD 0xe0000
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#define FA_SEL_RSP 0xf0000
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#define CTRL_BC_MASK 0x00001fff
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#define CTRL_AE ((uint32)3 << 16)
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#define CTRL_AE_SHIFT 16
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#define CTRL_PARITY ((uint32)3 << 18)
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#define CTRL_EOT ((uint32)1 << 28)
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#define CTRL_IOC ((uint32)1 << 29)
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#define CTRL_EOF ((uint32)1 << 30)
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#define CTRL_SOF ((uint32)1 << 31)
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#define CTRL_CORE_MASK 0x0ff00000
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typedef volatile struct {
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uint32 control;
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uint32 ptr;
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uint32 addrlow;
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uint32 addrhigh;
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uint32 status0;
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uint32 status1;
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} dma64regs_t;
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typedef volatile struct {
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dma64regs_t tx;
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dma64regs_t rx;
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} dma64regp_t;
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typedef volatile struct {
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uint32 fifoaddr;
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uint32 fifodatalow;
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uint32 fifodatahigh;
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uint32 pad;
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} dma64diag_t;
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typedef volatile struct {
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uint32 ctrl1;
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uint32 ctrl2;
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uint32 addrlow;
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uint32 addrhigh;
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} dma64dd_t;
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#define D64RINGALIGN_BITS 13
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#define D64MAXRINGSZ (1 << D64RINGALIGN_BITS)
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#define D64RINGALIGN (1 << D64RINGALIGN_BITS)
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#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
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#define D64_XC_XE 0x00000001
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#define D64_XC_SE 0x00000002
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#define D64_XC_LE 0x00000004
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#define D64_XC_FL 0x00000010
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#define D64_XC_MR_MASK 0x000000C0
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#define D64_XC_MR_SHIFT 6
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#define D64_XC_PD 0x00000800
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#define D64_XC_AE 0x00030000
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#define D64_XC_AE_SHIFT 16
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#define D64_XC_BL_MASK 0x001C0000
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#define D64_XC_BL_SHIFT 18
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#define D64_XC_PC_MASK 0x00E00000
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#define D64_XC_PC_SHIFT 21
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#define D64_XC_PT_MASK 0x03000000
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#define D64_XC_PT_SHIFT 24
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#define D64_XP_LD_MASK 0x00001fff
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#define D64_XS0_CD_MASK 0x00001fff
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#define D64_XS0_XS_MASK 0xf0000000
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#define D64_XS0_XS_SHIFT 28
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#define D64_XS0_XS_DISABLED 0x00000000
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#define D64_XS0_XS_ACTIVE 0x10000000
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#define D64_XS0_XS_IDLE 0x20000000
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#define D64_XS0_XS_STOPPED 0x30000000
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#define D64_XS0_XS_SUSP 0x40000000
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#define D64_XS1_AD_MASK 0x00001fff
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#define D64_XS1_XE_MASK 0xf0000000
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#define D64_XS1_XE_SHIFT 28
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#define D64_XS1_XE_NOERR 0x00000000
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#define D64_XS1_XE_DPE 0x10000000
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#define D64_XS1_XE_DFU 0x20000000
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#define D64_XS1_XE_DTE 0x30000000
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#define D64_XS1_XE_DESRE 0x40000000
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#define D64_XS1_XE_COREE 0x50000000
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#define D64_RC_RE 0x00000001
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#define D64_RC_RO_MASK 0x000000fe
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#define D64_RC_RO_SHIFT 1
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#define D64_RC_FM 0x00000100
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#define D64_RC_SH 0x00000200
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#define D64_RC_OC 0x00000400
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#define D64_RC_PD 0x00000800
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#define D64_RC_AE 0x00030000
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#define D64_RC_AE_SHIFT 16
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#define D64_RC_BL_MASK 0x001C0000
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#define D64_RC_BL_SHIFT 18
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#define D64_RC_PC_MASK 0x00E00000
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#define D64_RC_PC_SHIFT 21
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#define D64_RC_PT_MASK 0x03000000
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#define D64_RC_PT_SHIFT 24
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#define DMA_CTRL_PEN (1 << 0)
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#define DMA_CTRL_ROC (1 << 1)
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#define DMA_CTRL_RXMULTI (1 << 2)
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#define DMA_CTRL_UNFRAMED (1 << 3)
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#define DMA_CTRL_USB_BOUNDRY4KB_WAR (1 << 4)
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#define DMA_CTRL_DMA_AVOIDANCE_WAR (1 << 5)
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#define D64_RP_LD_MASK 0x00001fff
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#define D64_RS0_CD_MASK 0x00001fff
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#define D64_RS0_RS_MASK 0xf0000000
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#define D64_RS0_RS_SHIFT 28
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#define D64_RS0_RS_DISABLED 0x00000000
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#define D64_RS0_RS_ACTIVE 0x10000000
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#define D64_RS0_RS_IDLE 0x20000000
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#define D64_RS0_RS_STOPPED 0x30000000
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#define D64_RS0_RS_SUSP 0x40000000
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#define D64_RS1_AD_MASK 0x0001ffff
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#define D64_RS1_RE_MASK 0xf0000000
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#define D64_RS1_RE_SHIFT 28
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#define D64_RS1_RE_NOERR 0x00000000
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#define D64_RS1_RE_DPO 0x10000000
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#define D64_RS1_RE_DFU 0x20000000
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#define D64_RS1_RE_DTE 0x30000000
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#define D64_RS1_RE_DESRE 0x40000000
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#define D64_RS1_RE_COREE 0x50000000
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#define D64_FA_OFF_MASK 0xffff
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#define D64_FA_SEL_MASK 0xf0000
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#define D64_FA_SEL_SHIFT 16
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#define D64_FA_SEL_XDD 0x00000
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#define D64_FA_SEL_XDP 0x10000
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#define D64_FA_SEL_RDD 0x40000
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#define D64_FA_SEL_RDP 0x50000
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#define D64_FA_SEL_XFD 0x80000
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#define D64_FA_SEL_XFP 0x90000
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#define D64_FA_SEL_RFD 0xc0000
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#define D64_FA_SEL_RFP 0xd0000
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#define D64_FA_SEL_RSD 0xe0000
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#define D64_FA_SEL_RSP 0xf0000
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#define D64_CTRL_COREFLAGS 0x0ff00000
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#define D64_CTRL1_EOT ((uint32)1 << 28)
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#define D64_CTRL1_IOC ((uint32)1 << 29)
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#define D64_CTRL1_EOF ((uint32)1 << 30)
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#define D64_CTRL1_SOF ((uint32)1 << 31)
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#define D64_CTRL2_BC_MASK 0x00007fff
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#define D64_CTRL2_AE 0x00030000
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#define D64_CTRL2_AE_SHIFT 16
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#define D64_CTRL2_PARITY 0x00040000
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#define D64_CTRL_CORE_MASK 0x0ff00000
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#define D64_RX_FRM_STS_LEN 0x0000ffff
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#define D64_RX_FRM_STS_OVFL 0x00800000
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#define D64_RX_FRM_STS_DSCRCNT 0x0f000000
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#define D64_RX_FRM_STS_DATATYPE 0xf0000000
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typedef volatile struct {
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uint16 len;
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uint16 flags;
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} dma_rxh_t;
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#endif
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