279 lines
12 KiB
C
279 lines
12 KiB
C
#ifndef _IBM_LANA_INCLUDE_
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#define _IBM_LANA_INCLUDE_
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#ifdef _IBM_LANA_DRIVER_
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/* maximum packet size */
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#define PKTSIZE 1524
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/* number of transmit buffers */
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#define TXBUFCNT 4
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/* Adapter ID's */
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#define IBM_LANA_ID 0xffe0
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/* media enumeration - defined in a way that it fits onto the LAN/A's
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POS registers... */
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typedef enum {
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Media_10BaseT, Media_10Base5,
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Media_Unknown, Media_10Base2, Media_Count
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} ibmlana_medium;
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/* private structure */
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typedef struct {
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unsigned int slot; /* MCA-Slot-# */
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int realirq; /* memorizes actual IRQ, even when
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currently not allocated */
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ibmlana_medium medium; /* physical cannector */
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u32 tdastart, txbufstart, /* addresses */
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rrastart, rxbufstart, rdastart, rxbufcnt, txusedcnt;
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int nextrxdescr, /* next rx descriptor to be used */
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lastrxdescr, /* last free rx descriptor */
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nexttxdescr, /* last tx descriptor to be used */
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currtxdescr, /* tx descriptor currently tx'ed */
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txused[TXBUFCNT]; /* busy flags */
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void __iomem *base;
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spinlock_t lock;
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} ibmlana_priv;
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/* this card uses quite a lot of I/O ports...luckily the MCA bus decodes
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a full 64K I/O range... */
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#define IBM_LANA_IORANGE 0xa0
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/* Command Register: */
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#define SONIC_CMDREG 0x00
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#define CMDREG_HTX 0x0001 /* halt transmission */
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#define CMDREG_TXP 0x0002 /* start transmission */
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#define CMDREG_RXDIS 0x0004 /* disable receiver */
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#define CMDREG_RXEN 0x0008 /* enable receiver */
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#define CMDREG_STP 0x0010 /* stop timer */
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#define CMDREG_ST 0x0020 /* start timer */
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#define CMDREG_RST 0x0080 /* software reset */
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#define CMDREG_RRRA 0x0100 /* force SONIC to read first RRA */
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#define CMDREG_LCAM 0x0200 /* force SONIC to read CAM descrs */
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/* Data Configuration Register */
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#define SONIC_DCREG 0x02
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#define DCREG_EXBUS 0x8000 /* Extended Bus Mode */
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#define DCREG_LBR 0x2000 /* Latched Bus Retry */
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#define DCREG_PO1 0x1000 /* Programmable Outputs */
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#define DCREG_PO0 0x0800
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#define DCREG_SBUS 0x0400 /* Synchronous Bus Mode */
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#define DCREG_USR1 0x0200 /* User Definable Pins */
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#define DCREG_USR0 0x0100
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#define DCREG_WC0 0x0000 /* 0..3 Wait States */
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#define DCREG_WC1 0x0040
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#define DCREG_WC2 0x0080
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#define DCREG_WC3 0x00c0
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#define DCREG_DW16 0x0000 /* 16 bit Bus Mode */
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#define DCREG_DW32 0x0020 /* 32 bit Bus Mode */
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#define DCREG_BMS 0x0010 /* Block Mode Select */
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#define DCREG_RFT4 0x0000 /* 4/8/16/24 bytes RX Threshold */
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#define DCREG_RFT8 0x0004
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#define DCREG_RFT16 0x0008
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#define DCREG_RFT24 0x000c
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#define DCREG_TFT8 0x0000 /* 8/16/24/28 bytes TX Threshold */
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#define DCREG_TFT16 0x0001
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#define DCREG_TFT24 0x0002
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#define DCREG_TFT28 0x0003
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/* Receive Control Register */
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#define SONIC_RCREG 0x04
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#define RCREG_ERR 0x8000 /* accept damaged and collided pkts */
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#define RCREG_RNT 0x4000 /* accept packets that are < 64 */
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#define RCREG_BRD 0x2000 /* accept broadcasts */
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#define RCREG_PRO 0x1000 /* promiscuous mode */
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#define RCREG_AMC 0x0800 /* accept all multicasts */
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#define RCREG_LB_NONE 0x0000 /* no loopback */
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#define RCREG_LB_MAC 0x0200 /* MAC loopback */
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#define RCREG_LB_ENDEC 0x0400 /* ENDEC loopback */
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#define RCREG_LB_XVR 0x0600 /* Transceiver loopback */
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#define RCREG_MC 0x0100 /* Multicast received */
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#define RCREG_BC 0x0080 /* Broadcast received */
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#define RCREG_LPKT 0x0040 /* last packet in RBA */
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#define RCREG_CRS 0x0020 /* carrier sense present */
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#define RCREG_COL 0x0010 /* recv'd packet with collision */
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#define RCREG_CRCR 0x0008 /* recv'd packet with CRC error */
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#define RCREG_FAER 0x0004 /* recv'd packet with inv. framing */
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#define RCREG_LBK 0x0002 /* recv'd loopback packet */
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#define RCREG_PRX 0x0001 /* recv'd packet is OK */
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/* Transmit Control Register */
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#define SONIC_TCREG 0x06
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#define TCREG_PINT 0x8000 /* generate interrupt after TDA read */
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#define TCREG_POWC 0x4000 /* timer start out of window detect */
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#define TCREG_CRCI 0x2000 /* inhibit CRC generation */
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#define TCREG_EXDIS 0x1000 /* disable excessive deferral timer */
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#define TCREG_EXD 0x0400 /* excessive deferral occurred */
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#define TCREG_DEF 0x0200 /* single deferral occurred */
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#define TCREG_NCRS 0x0100 /* no carrier detected */
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#define TCREG_CRSL 0x0080 /* carrier lost */
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#define TCREG_EXC 0x0040 /* excessive collisions occurred */
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#define TCREG_OWC 0x0020 /* out of window collision occurred */
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#define TCREG_PMB 0x0008 /* packet monitored bad */
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#define TCREG_FU 0x0004 /* FIFO underrun */
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#define TCREG_BCM 0x0002 /* byte count mismatch of fragments */
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#define TCREG_PTX 0x0001 /* packet transmitted OK */
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/* Interrupt Mask Register */
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#define SONIC_IMREG 0x08
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#define IMREG_BREN 0x4000 /* interrupt when bus retry occurred */
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#define IMREG_HBLEN 0x2000 /* interrupt when heartbeat lost */
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#define IMREG_LCDEN 0x1000 /* interrupt when CAM loaded */
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#define IMREG_PINTEN 0x0800 /* interrupt when PINT in TDA set */
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#define IMREG_PRXEN 0x0400 /* interrupt when packet received */
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#define IMREG_PTXEN 0x0200 /* interrupt when packet was sent */
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#define IMREG_TXEREN 0x0100 /* interrupt when send failed */
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#define IMREG_TCEN 0x0080 /* interrupt when timer completed */
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#define IMREG_RDEEN 0x0040 /* interrupt when RDA exhausted */
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#define IMREG_RBEEN 0x0020 /* interrupt when RBA exhausted */
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#define IMREG_RBAEEN 0x0010 /* interrupt when RBA too short */
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#define IMREG_CRCEN 0x0008 /* interrupt when CRC counter rolls */
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#define IMREG_FAEEN 0x0004 /* interrupt when FAE counter rolls */
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#define IMREG_MPEN 0x0002 /* interrupt when MP counter rolls */
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#define IMREG_RFOEN 0x0001 /* interrupt when Rx FIFO overflows */
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/* Interrupt Status Register */
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#define SONIC_ISREG 0x0a
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#define ISREG_BR 0x4000 /* bus retry occurred */
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#define ISREG_HBL 0x2000 /* heartbeat lost */
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#define ISREG_LCD 0x1000 /* CAM loaded */
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#define ISREG_PINT 0x0800 /* PINT in TDA set */
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#define ISREG_PKTRX 0x0400 /* packet received */
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#define ISREG_TXDN 0x0200 /* packet was sent */
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#define ISREG_TXER 0x0100 /* send failed */
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#define ISREG_TC 0x0080 /* timer completed */
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#define ISREG_RDE 0x0040 /* RDA exhausted */
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#define ISREG_RBE 0x0020 /* RBA exhausted */
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#define ISREG_RBAE 0x0010 /* RBA too short for received frame */
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#define ISREG_CRC 0x0008 /* CRC counter rolls over */
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#define ISREG_FAE 0x0004 /* FAE counter rolls over */
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#define ISREG_MP 0x0002 /* MP counter rolls over */
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#define ISREG_RFO 0x0001 /* Rx FIFO overflows */
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#define SONIC_UTDA 0x0c /* current transmit descr address */
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#define SONIC_CTDA 0x0e
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#define SONIC_URDA 0x1a /* current receive descr address */
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#define SONIC_CRDA 0x1c
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#define SONIC_CRBA0 0x1e /* current receive buffer address */
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#define SONIC_CRBA1 0x20
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#define SONIC_RBWC0 0x22 /* word count in receive buffer */
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#define SONIC_RBWC1 0x24
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#define SONIC_EOBC 0x26 /* minimum space to be free in RBA */
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#define SONIC_URRA 0x28 /* upper address of CDA & Recv Area */
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#define SONIC_RSA 0x2a /* start of receive resource area */
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#define SONIC_REA 0x2c /* end of receive resource area */
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#define SONIC_RRP 0x2e /* resource read pointer */
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#define SONIC_RWP 0x30 /* resource write pointer */
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#define SONIC_CAMEPTR 0x42 /* CAM entry pointer */
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#define SONIC_CAMADDR2 0x44 /* CAM address ports */
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#define SONIC_CAMADDR1 0x46
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#define SONIC_CAMADDR0 0x48
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#define SONIC_CAMPTR 0x4c /* lower address of CDA */
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#define SONIC_CAMCNT 0x4e /* # of CAM descriptors to load */
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/* Data Configuration Register 2 */
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#define SONIC_DCREG2 0x7e
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#define DCREG2_EXPO3 0x8000 /* extended programmable outputs */
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#define DCREG2_EXPO2 0x4000
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#define DCREG2_EXPO1 0x2000
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#define DCREG2_EXPO0 0x1000
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#define DCREG2_HD 0x0800 /* heartbeat disable */
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#define DCREG2_JD 0x0200 /* jabber timer disable */
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#define DCREG2_AUTO 0x0100 /* enable AUI/TP auto selection */
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#define DCREG2_XWRAP 0x0040 /* TP transceiver loopback */
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#define DCREG2_PH 0x0010 /* HOLD request timing */
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#define DCREG2_PCM 0x0004 /* packet compress when matched */
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#define DCREG2_PCNM 0x0002 /* packet compress when not matched */
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#define DCREG2_RJCM 0x0001 /* inverse packet match via CAM */
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/* Board Control Register: Enable RAM, Interrupts... */
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#define BCMREG 0x80
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#define BCMREG_RAMEN 0x80 /* switch over to RAM */
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#define BCMREG_IPEND 0x40 /* interrupt pending ? */
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#define BCMREG_RESET 0x08 /* reset board */
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#define BCMREG_16BIT 0x04 /* adapter in 16-bit slot */
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#define BCMREG_RAMWIN 0x02 /* enable RAM window */
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#define BCMREG_IEN 0x01 /* interrupt enable */
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/* MAC Address PROM */
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#define MACADDRPROM 0x92
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/* structure of a CAM entry */
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typedef struct {
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u32 index; /* pointer into CAM area */
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u32 addr0; /* address part (bits 0..15 used) */
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u32 addr1;
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u32 addr2;
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} camentry_t;
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/* structure of a receive resource */
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typedef struct {
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u32 startlo; /* start address (bits 0..15 used) */
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u32 starthi;
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u32 cntlo; /* size in 16-bit quantities */
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u32 cnthi;
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} rra_t;
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/* structure of a receive descriptor */
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typedef struct {
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u32 status; /* packet status */
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u32 length; /* length in bytes */
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u32 startlo; /* start address */
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u32 starthi;
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u32 seqno; /* frame sequence */
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u32 link; /* pointer to next descriptor */
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/* bit 0 = EOL */
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u32 inuse; /* !=0 --> free for SONIC to write */
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} rda_t;
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/* structure of a transmit descriptor */
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typedef struct {
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u32 status; /* transmit status */
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u32 config; /* value for TCR */
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u32 length; /* total length */
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u32 fragcount; /* number of fragments */
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u32 startlo; /* start address of fragment */
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u32 starthi;
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u32 fraglength; /* length of this fragment */
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/* more address/length triplets may */
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/* follow here */
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u32 link; /* pointer to next descriptor */
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/* bit 0 = EOL */
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} tda_t;
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#endif /* _IBM_LANA_DRIVER_ */
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#endif /* _IBM_LANA_INCLUDE_ */
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