539 lines
15 KiB
C
539 lines
15 KiB
C
/*
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* linux/drivers/mmc/host/msmsdcc.h - QCT MSM7K SDC Controller
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*
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* Copyright (C) 2008 Google, All Rights Reserved.
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* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* - Based on mmci.h
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*/
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#ifndef _MSM_SDCC_H
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#define _MSM_SDCC_H
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/sdio.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-mapping.h>
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#include <linux/wakelock.h>
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#include <linux/pm_qos.h>
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#include <mach/sps.h>
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#include <asm/sizes.h>
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#include <asm/mach/mmc.h>
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#include <mach/dma.h>
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#define MMCIPOWER 0x000
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#define MCI_PWR_OFF 0x00
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#define MCI_PWR_UP 0x02
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#define MCI_PWR_ON 0x03
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#define MCI_OD (1 << 6)
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#define MCI_SW_RST (1 << 7)
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#define MCI_SW_RST_CFG (1 << 8)
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#define MMCICLOCK 0x004
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#define MCI_CLK_ENABLE (1 << 8)
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#define MCI_CLK_PWRSAVE (1 << 9)
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#define MCI_CLK_WIDEBUS_1 (0 << 10)
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#define MCI_CLK_WIDEBUS_4 (2 << 10)
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#define MCI_CLK_WIDEBUS_8 (3 << 10)
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#define MCI_CLK_FLOWENA (1 << 12)
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#define MCI_CLK_INVERTOUT (1 << 13)
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#define MCI_CLK_SELECTIN (1 << 15)
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#define IO_PAD_PWR_SWITCH (1 << 21)
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#define MMCIARGUMENT 0x008
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#define MMCICOMMAND 0x00c
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#define MCI_CPSM_RESPONSE (1 << 6)
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#define MCI_CPSM_LONGRSP (1 << 7)
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#define MCI_CPSM_INTERRUPT (1 << 8)
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#define MCI_CPSM_PENDING (1 << 9)
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#define MCI_CPSM_ENABLE (1 << 10)
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#define MCI_CPSM_PROGENA (1 << 11)
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#define MCI_CSPM_DATCMD (1 << 12)
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#define MCI_CSPM_MCIABORT (1 << 13)
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#define MCI_CSPM_CCSENABLE (1 << 14)
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#define MCI_CSPM_CCSDISABLE (1 << 15)
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#define MCI_CSPM_AUTO_CMD19 (1 << 16)
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#define MCI_CSPM_AUTO_CMD21 (1 << 21)
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#define MMCIRESPCMD 0x010
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#define MMCIRESPONSE0 0x014
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#define MMCIRESPONSE1 0x018
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#define MMCIRESPONSE2 0x01c
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#define MMCIRESPONSE3 0x020
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#define MMCIDATATIMER 0x024
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#define MMCIDATALENGTH 0x028
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#define MMCIDATACTRL 0x02c
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#define MCI_DPSM_ENABLE (1 << 0)
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#define MCI_DPSM_DIRECTION (1 << 1)
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#define MCI_DPSM_MODE (1 << 2)
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#define MCI_DPSM_DMAENABLE (1 << 3)
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#define MCI_DATA_PEND (1 << 17)
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#define MCI_AUTO_PROG_DONE (1 << 19)
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#define MCI_RX_DATA_PEND (1 << 20)
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#define MMCIDATACNT 0x030
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#define MMCISTATUS 0x034
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#define MCI_CMDCRCFAIL (1 << 0)
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#define MCI_DATACRCFAIL (1 << 1)
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#define MCI_CMDTIMEOUT (1 << 2)
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#define MCI_DATATIMEOUT (1 << 3)
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#define MCI_TXUNDERRUN (1 << 4)
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#define MCI_RXOVERRUN (1 << 5)
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#define MCI_CMDRESPEND (1 << 6)
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#define MCI_CMDSENT (1 << 7)
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#define MCI_DATAEND (1 << 8)
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#define MCI_DATABLOCKEND (1 << 10)
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#define MCI_CMDACTIVE (1 << 11)
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#define MCI_TXACTIVE (1 << 12)
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#define MCI_RXACTIVE (1 << 13)
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#define MCI_TXFIFOHALFEMPTY (1 << 14)
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#define MCI_RXFIFOHALFFULL (1 << 15)
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#define MCI_TXFIFOFULL (1 << 16)
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#define MCI_RXFIFOFULL (1 << 17)
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#define MCI_TXFIFOEMPTY (1 << 18)
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#define MCI_RXFIFOEMPTY (1 << 19)
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#define MCI_TXDATAAVLBL (1 << 20)
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#define MCI_RXDATAAVLBL (1 << 21)
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#define MCI_SDIOINTR (1 << 22)
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#define MCI_PROGDONE (1 << 23)
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#define MCI_ATACMDCOMPL (1 << 24)
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#define MCI_SDIOINTROPE (1 << 25)
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#define MCI_CCSTIMEOUT (1 << 26)
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#define MCI_AUTOCMD19TIMEOUT (1 << 30)
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#define MMCICLEAR 0x038
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#define MCI_CMDCRCFAILCLR (1 << 0)
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#define MCI_DATACRCFAILCLR (1 << 1)
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#define MCI_CMDTIMEOUTCLR (1 << 2)
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#define MCI_DATATIMEOUTCLR (1 << 3)
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#define MCI_TXUNDERRUNCLR (1 << 4)
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#define MCI_RXOVERRUNCLR (1 << 5)
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#define MCI_CMDRESPENDCLR (1 << 6)
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#define MCI_CMDSENTCLR (1 << 7)
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#define MCI_DATAENDCLR (1 << 8)
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#define MCI_STARTBITERRCLR (1 << 9)
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#define MCI_DATABLOCKENDCLR (1 << 10)
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#define MCI_SDIOINTRCLR (1 << 22)
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#define MCI_PROGDONECLR (1 << 23)
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#define MCI_ATACMDCOMPLCLR (1 << 24)
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#define MCI_SDIOINTROPECLR (1 << 25)
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#define MCI_CCSTIMEOUTCLR (1 << 26)
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#define MCI_CLEAR_STATIC_MASK \
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(MCI_CMDCRCFAILCLR|MCI_DATACRCFAILCLR|MCI_CMDTIMEOUTCLR|\
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MCI_DATATIMEOUTCLR|MCI_TXUNDERRUNCLR|MCI_RXOVERRUNCLR| \
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MCI_CMDRESPENDCLR|MCI_CMDSENTCLR|MCI_DATAENDCLR| \
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MCI_STARTBITERRCLR|MCI_DATABLOCKENDCLR|MCI_SDIOINTRCLR| \
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MCI_SDIOINTROPECLR|MCI_PROGDONECLR|MCI_ATACMDCOMPLCLR| \
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MCI_CCSTIMEOUTCLR)
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#define MMCIMASK0 0x03c
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#define MCI_CMDCRCFAILMASK (1 << 0)
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#define MCI_DATACRCFAILMASK (1 << 1)
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#define MCI_CMDTIMEOUTMASK (1 << 2)
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#define MCI_DATATIMEOUTMASK (1 << 3)
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#define MCI_TXUNDERRUNMASK (1 << 4)
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#define MCI_RXOVERRUNMASK (1 << 5)
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#define MCI_CMDRESPENDMASK (1 << 6)
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#define MCI_CMDSENTMASK (1 << 7)
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#define MCI_DATAENDMASK (1 << 8)
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#define MCI_DATABLOCKENDMASK (1 << 10)
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#define MCI_CMDACTIVEMASK (1 << 11)
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#define MCI_TXACTIVEMASK (1 << 12)
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#define MCI_RXACTIVEMASK (1 << 13)
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#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
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#define MCI_RXFIFOHALFFULLMASK (1 << 15)
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#define MCI_TXFIFOFULLMASK (1 << 16)
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#define MCI_RXFIFOFULLMASK (1 << 17)
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#define MCI_TXFIFOEMPTYMASK (1 << 18)
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#define MCI_RXFIFOEMPTYMASK (1 << 19)
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#define MCI_TXDATAAVLBLMASK (1 << 20)
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#define MCI_RXDATAAVLBLMASK (1 << 21)
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#define MCI_SDIOINTMASK (1 << 22)
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#define MCI_PROGDONEMASK (1 << 23)
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#define MCI_ATACMDCOMPLMASK (1 << 24)
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#define MCI_SDIOINTOPERMASK (1 << 25)
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#define MCI_CCSTIMEOUTMASK (1 << 26)
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#define MCI_AUTOCMD19TIMEOUTMASK (1 << 30)
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#define MMCIMASK1 0x040
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#define MMCIFIFOCNT 0x044
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#define MCI_VERSION 0x050
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#define MCICCSTIMER 0x058
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#define MCI_DLL_CONFIG 0x060
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#define MCI_DLL_EN (1 << 16)
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#define MCI_CDR_EN (1 << 17)
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#define MCI_CK_OUT_EN (1 << 18)
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#define MCI_CDR_EXT_EN (1 << 19)
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#define MCI_DLL_PDN (1 << 29)
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#define MCI_DLL_RST (1 << 30)
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#define MCI_DLL_STATUS 0x068
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#define MCI_DLL_LOCK (1 << 7)
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#define MCI_STATUS2 0x06C
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#define MCI_MCLK_REG_WR_ACTIVE (1 << 0)
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#define MMCIFIFO 0x080 /* to 0x0bc */
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#define MCI_TEST_INPUT 0x0D4
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#define MCI_TESTBUS_CONFIG 0x0CC
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#define MCI_TESTBUS_SEL_MASK (0x7)
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#define MAX_TESTBUS 8
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#define MCI_TESTBUS_ENA (1 << 3)
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#define MCI_SDCC_DEBUG_REG 0x124
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#define MCI_IRQENABLE \
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(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
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MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
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MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATAENDMASK| \
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MCI_PROGDONEMASK|MCI_AUTOCMD19TIMEOUTMASK)
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#define MCI_IRQ_PIO \
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(MCI_RXDATAAVLBLMASK | MCI_TXDATAAVLBLMASK | \
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MCI_RXFIFOEMPTYMASK | MCI_TXFIFOEMPTYMASK | MCI_RXFIFOFULLMASK |\
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MCI_TXFIFOFULLMASK | MCI_RXFIFOHALFFULLMASK | \
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MCI_TXFIFOHALFEMPTYMASK | MCI_RXACTIVEMASK | MCI_TXACTIVEMASK)
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/*
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* The size of the FIFO in bytes.
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*/
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#define MCI_FIFOSIZE (16*4)
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#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
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#define NR_SG 128
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#define MSM_MMC_DEFAULT_IDLE_TIMEOUT 5000 /* msecs */
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#define MSM_MMC_CLK_GATE_DELAY 200 /* msecs */
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/* Set the request timeout to 10secs */
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#define MSM_MMC_REQ_TIMEOUT 10000 /* msecs */
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/*
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* Controller HW limitations
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*/
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#define MCI_DATALENGTH_BITS 25
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#define MMC_MAX_REQ_SIZE ((1 << MCI_DATALENGTH_BITS) - 1)
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/* MCI_DATA_CTL BLOCKSIZE up to 4096 */
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#define MMC_MAX_BLK_SIZE 4096
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#define MMC_MIN_BLK_SIZE 512
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#define MMC_MAX_BLK_CNT (MMC_MAX_REQ_SIZE / MMC_MIN_BLK_SIZE)
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/* 64KiB */
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#define MAX_SG_SIZE (64 * 1024)
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#define MAX_NR_SG_DMA_PIO (MMC_MAX_REQ_SIZE / MAX_SG_SIZE)
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/*
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* BAM limitations
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*/
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/* upto 16 bits (64K - 1) */
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#define SPS_MAX_DESC_FIFO_SIZE 65535
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/* 16KiB */
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#define SPS_MAX_DESC_SIZE (16 * 1024)
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/* Each descriptor is of length 8 bytes */
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#define SPS_MAX_DESC_LENGTH 8
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#define SPS_MAX_DESCS (SPS_MAX_DESC_FIFO_SIZE / SPS_MAX_DESC_LENGTH)
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/*
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* DMA limitations
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*/
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/* upto 16 bits (64K - 1) */
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#define MMC_MAX_DMA_ROWS (64 * 1024 - 1)
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#define MMC_MAX_DMA_BOX_LENGTH (MMC_MAX_DMA_ROWS * MCI_FIFOSIZE)
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#define MMC_MAX_DMA_CMDS (MAX_NR_SG_DMA_PIO * (MMC_MAX_REQ_SIZE / \
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MMC_MAX_DMA_BOX_LENGTH))
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/*
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* Peripheral bus clock scaling vote rates
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*/
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#define MSMSDCC_BUS_VOTE_MAX_RATE 64000000 /* Hz */
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#define MSMSDCC_BUS_VOTE_MIN_RATE 32000000 /* Hz */
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struct clk;
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struct msmsdcc_nc_dmadata {
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dmov_box cmd[MMC_MAX_DMA_CMDS];
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uint32_t cmdptr;
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};
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struct msmsdcc_dma_data {
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struct msmsdcc_nc_dmadata *nc;
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dma_addr_t nc_busaddr;
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dma_addr_t cmd_busaddr;
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dma_addr_t cmdptr_busaddr;
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struct msm_dmov_cmd hdr;
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enum dma_data_direction dir;
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struct scatterlist *sg;
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int num_ents;
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int channel;
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int crci;
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struct msmsdcc_host *host;
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int busy; /* Set if DM is busy */
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unsigned int result;
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struct msm_dmov_errdata err;
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};
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struct msmsdcc_pio_data {
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struct sg_mapping_iter sg_miter;
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char bounce_buf[4];
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/* valid bytes in bounce_buf */
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int bounce_buf_len;
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};
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struct msmsdcc_curr_req {
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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unsigned int xfer_size; /* Total data size */
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unsigned int xfer_remain; /* Bytes remaining to send */
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unsigned int data_xfered; /* Bytes acked by BLKEND irq */
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int got_dataend;
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bool wait_for_auto_prog_done;
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bool got_auto_prog_done;
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bool use_wr_data_pend;
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int user_pages;
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u32 req_tout_ms;
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};
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struct msmsdcc_sps_ep_conn_data {
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struct sps_pipe *pipe_handle;
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struct sps_connect config;
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struct sps_register_event event;
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};
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struct msmsdcc_sps_data {
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struct msmsdcc_sps_ep_conn_data prod;
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struct msmsdcc_sps_ep_conn_data cons;
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struct sps_event_notify notify;
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enum dma_data_direction dir;
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struct scatterlist *sg;
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int num_ents;
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u32 bam_handle;
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unsigned int src_pipe_index;
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unsigned int dest_pipe_index;
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unsigned int busy;
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unsigned int xfer_req_cnt;
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bool reset_bam;
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struct tasklet_struct tlet;
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};
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struct msmsdcc_msm_bus_vote {
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uint32_t client_handle;
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uint32_t curr_vote;
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int min_bw_vote;
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int max_bw_vote;
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bool is_max_bw_needed;
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struct delayed_work vote_work;
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};
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struct msmsdcc_host {
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struct resource *core_irqres;
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struct resource *bam_irqres;
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struct resource *core_memres;
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struct resource *bam_memres;
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struct resource *dml_memres;
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struct resource *dmares;
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struct resource *dma_crci_res;
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void __iomem *base;
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void __iomem *dml_base;
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void __iomem *bam_base;
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struct platform_device *pdev;
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struct msmsdcc_curr_req curr;
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struct mmc_host *mmc;
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struct clk *clk; /* main MMC bus clock */
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struct clk *pclk; /* SDCC peripheral bus clock */
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struct clk *bus_clk; /* SDCC bus voter clock */
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unsigned long bus_clk_rate; /* peripheral bus clk rate */
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atomic_t clks_on; /* set if clocks are enabled */
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unsigned int eject; /* eject state */
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spinlock_t lock;
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unsigned int clk_rate; /* Current clock rate */
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unsigned int pclk_rate;
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u32 pwr;
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struct mmc_platform_data *plat;
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unsigned int hw_caps;
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unsigned int oldstat;
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struct msmsdcc_dma_data dma;
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struct msmsdcc_sps_data sps;
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struct msmsdcc_pio_data pio;
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struct tasklet_struct dma_tlet;
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unsigned int prog_enable;
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/* Command parameters */
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unsigned int cmd_timeout;
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unsigned int cmd_pio_irqmask;
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unsigned int cmd_datactrl;
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struct mmc_command *cmd_cmd;
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u32 cmd_c;
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unsigned int mci_irqenable;
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unsigned int dummy_52_needed;
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unsigned int dummy_52_sent;
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struct wake_lock sdio_wlock;
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struct wake_lock sdio_suspend_wlock;
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struct timer_list req_tout_timer;
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unsigned long reg_write_delay;
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bool io_pad_pwr_switch;
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bool tuning_in_progress;
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bool tuning_needed;
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bool tuning_done;
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bool en_auto_cmd19;
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bool en_auto_cmd21;
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bool sdio_gpio_lpm;
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bool irq_wake_enabled;
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struct pm_qos_request pm_qos_req_dma;
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u32 cpu_dma_latency;
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bool sdcc_suspending;
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bool sdcc_irq_disabled;
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bool sdcc_suspended;
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bool sdio_wakeupirq_disabled;
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struct mutex clk_mutex;
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bool pending_resume;
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unsigned int idle_tout; /* Timeout in msecs */
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bool enforce_pio_mode;
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bool print_pm_stats;
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struct msmsdcc_msm_bus_vote msm_bus_vote;
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struct device_attribute max_bus_bw;
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struct device_attribute polling;
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struct device_attribute idle_timeout;
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struct device_attribute auto_cmd19_attr;
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struct device_attribute auto_cmd21_attr;
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struct dentry *debugfs_host_dir;
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struct dentry *debugfs_idle_tout;
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struct dentry *debugfs_pio_mode;
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struct dentry *debugfs_pm_stats;
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int saved_tuning_phase;
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};
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#define MSMSDCC_VERSION_STEP_MASK 0x0000FFFF
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#define MSMSDCC_VERSION_MINOR_MASK 0x0FFF0000
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#define MSMSDCC_VERSION_MINOR_SHIFT 16
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#define MSMSDCC_VERSION_MAJOR_MASK 0xF0000000
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#define MSMSDCC_VERSION_MAJOR_SHIFT 28
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#define MSMSDCC_DMA_SUP (1 << 0)
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#define MSMSDCC_SPS_BAM_SUP (1 << 1)
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#define MSMSDCC_SOFT_RESET (1 << 2)
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#define MSMSDCC_AUTO_PROG_DONE (1 << 3)
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#define MSMSDCC_REG_WR_ACTIVE (1 << 4)
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#define MSMSDCC_SW_RST (1 << 5)
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#define MSMSDCC_SW_RST_CFG (1 << 6)
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#define MSMSDCC_WAIT_FOR_TX_RX (1 << 7)
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#define MSMSDCC_IO_PAD_PWR_SWITCH (1 << 8)
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#define MSMSDCC_AUTO_CMD19 (1 << 9)
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#define MSMSDCC_AUTO_CMD21 (1 << 10)
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#define MSMSDCC_SW_RST_CFG_BROKEN (1 << 11)
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#define MSMSDCC_DATA_PEND_FOR_CMD53 (1 << 12)
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#define MSMSDCC_TESTBUS_DEBUG (1 << 13)
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#define set_hw_caps(h, val) ((h)->hw_caps |= val)
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#define is_sps_mode(h) ((h)->hw_caps & MSMSDCC_SPS_BAM_SUP)
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#define is_dma_mode(h) ((h)->hw_caps & MSMSDCC_DMA_SUP)
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#define is_soft_reset(h) ((h)->hw_caps & MSMSDCC_SOFT_RESET)
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#define is_auto_prog_done(h) ((h)->hw_caps & MSMSDCC_AUTO_PROG_DONE)
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#define is_wait_for_reg_write(h) ((h)->hw_caps & MSMSDCC_REG_WR_ACTIVE)
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#define is_sw_hard_reset(h) ((h)->hw_caps & MSMSDCC_SW_RST)
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#define is_sw_reset_save_config(h) ((h)->hw_caps & MSMSDCC_SW_RST_CFG)
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#define is_wait_for_tx_rx_active(h) ((h)->hw_caps & MSMSDCC_WAIT_FOR_TX_RX)
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#define is_io_pad_pwr_switch(h) ((h)->hw_caps & MSMSDCC_IO_PAD_PWR_SWITCH)
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#define is_auto_cmd19(h) ((h)->hw_caps & MSMSDCC_AUTO_CMD19)
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#define is_auto_cmd21(h) ((h)->hw_caps & MSMSDCC_AUTO_CMD21)
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#define is_sw_reset_save_config_broken(h) \
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((h)->hw_caps & MSMSDCC_SW_RST_CFG_BROKEN)
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#define is_data_pend_for_cmd53(h) ((h)->hw_caps & MSMSDCC_DATA_PEND_FOR_CMD53)
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#define is_testbus_debug(h) ((h)->hw_caps & MSMSDCC_TESTBUS_DEBUG)
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/* Set controller capabilities based on version */
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static inline void set_default_hw_caps(struct msmsdcc_host *host)
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{
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u32 version;
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u16 step, minor;
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/*
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* Lookup the Controller Version, to identify the supported features
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* Version number read as 0 would indicate SDCC3 or earlier versions.
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*/
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version = readl_relaxed(host->base + MCI_VERSION);
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pr_info("%s: SDCC Version: 0x%.8x\n", mmc_hostname(host->mmc), version);
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if (!version)
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return;
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step = version & MSMSDCC_VERSION_STEP_MASK;
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minor = (version & MSMSDCC_VERSION_MINOR_MASK) >>
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MSMSDCC_VERSION_MINOR_SHIFT;
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if (version) /* SDCC v4 and greater */
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host->hw_caps |= MSMSDCC_AUTO_PROG_DONE |
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MSMSDCC_SOFT_RESET | MSMSDCC_REG_WR_ACTIVE
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| MSMSDCC_WAIT_FOR_TX_RX | MSMSDCC_IO_PAD_PWR_SWITCH
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| MSMSDCC_AUTO_CMD19;
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if ((step == 0x18) && (minor >= 3)) {
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host->hw_caps |= MSMSDCC_AUTO_CMD21;
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/* Version 0x06000018 need hard reset on errors */
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host->hw_caps &= ~MSMSDCC_SOFT_RESET;
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}
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if (step >= 0x2b) /* SDCC v4 2.1.0 and greater */
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host->hw_caps |= MSMSDCC_SW_RST | MSMSDCC_SW_RST_CFG |
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MSMSDCC_AUTO_CMD21 |
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MSMSDCC_DATA_PEND_FOR_CMD53 |
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MSMSDCC_TESTBUS_DEBUG |
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MSMSDCC_SW_RST_CFG_BROKEN;
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}
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int msmsdcc_set_pwrsave(struct mmc_host *mmc, int pwrsave);
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int msmsdcc_sdio_al_lpm(struct mmc_host *mmc, bool enable);
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#ifdef CONFIG_MSM_SDIO_AL
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static inline int msmsdcc_lpm_enable(struct mmc_host *mmc)
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{
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return msmsdcc_sdio_al_lpm(mmc, true);
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}
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static inline int msmsdcc_lpm_disable(struct mmc_host *mmc)
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{
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struct msmsdcc_host *host = mmc_priv(mmc);
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int ret;
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ret = msmsdcc_sdio_al_lpm(mmc, false);
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wake_unlock(&host->sdio_wlock);
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return ret;
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}
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#endif
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#endif
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