207 lines
6.2 KiB
C
207 lines
6.2 KiB
C
/* Copyright (c) 2002,2007-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ADRENO_DRAWCTXT_H
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#define __ADRENO_DRAWCTXT_H
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#include <linux/sched.h>
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#include "adreno_pm4types.h"
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#include "a2xx_reg.h"
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/* Flags */
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#define CTXT_FLAGS_NOT_IN_USE 0x00000000
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#define CTXT_FLAGS_IN_USE BIT(0)
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/* state shadow memory allocated */
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#define CTXT_FLAGS_STATE_SHADOW BIT(1)
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/* gmem shadow memory allocated */
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#define CTXT_FLAGS_GMEM_SHADOW BIT(2)
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/* gmem must be copied to shadow */
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#define CTXT_FLAGS_GMEM_SAVE BIT(3)
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/* gmem can be restored from shadow */
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#define CTXT_FLAGS_GMEM_RESTORE BIT(4)
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/* preamble packed in cmdbuffer for context switching */
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#define CTXT_FLAGS_PREAMBLE BIT(5)
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/* shader must be copied to shadow */
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#define CTXT_FLAGS_SHADER_SAVE BIT(6)
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/* shader can be restored from shadow */
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#define CTXT_FLAGS_SHADER_RESTORE BIT(7)
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/* Context has caused a GPU hang */
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#define CTXT_FLAGS_GPU_HANG BIT(8)
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/* Specifies there is no need to save GMEM */
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#define CTXT_FLAGS_NOGMEMALLOC BIT(9)
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/* Trash state for context */
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#define CTXT_FLAGS_TRASHSTATE BIT(10)
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/* per context timestamps enabled */
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#define CTXT_FLAGS_PER_CONTEXT_TS BIT(11)
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/* Context has caused a GPU hang and fault tolerance successful */
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#define CTXT_FLAGS_GPU_HANG_FT BIT(12)
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/* Context is being destroyed so dont save it */
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#define CTXT_FLAGS_BEING_DESTROYED BIT(13)
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/* User mode generated timestamps enabled */
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#define CTXT_FLAGS_USER_GENERATED_TS BIT(14)
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/* Context skip till EOF */
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#define CTXT_FLAGS_SKIP_EOF BIT(15)
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/* Context no fault tolerance */
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#define CTXT_FLAGS_NO_FAULT_TOLERANCE BIT(16)
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/* Symbolic table for the adreno draw context type */
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#define ADRENO_DRAWCTXT_TYPES \
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{ KGSL_CONTEXT_TYPE_ANY, "any" }, \
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{ KGSL_CONTEXT_TYPE_GL, "GL" }, \
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{ KGSL_CONTEXT_TYPE_CL, "CL" }, \
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{ KGSL_CONTEXT_TYPE_C2D, "C2D" }, \
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{ KGSL_CONTEXT_TYPE_RS, "RS" }
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struct kgsl_device;
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struct adreno_device;
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struct kgsl_device_private;
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struct kgsl_context;
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/* draw context */
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struct gmem_shadow_t {
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struct kgsl_memdesc gmemshadow; /* Shadow buffer address */
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/*
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* 256 KB GMEM surface = 4 bytes-per-pixel x 256 pixels/row x
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* 256 rows. Width & height must be multiples of 32 in case tiled
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* textures are used
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*/
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enum COLORFORMATX format; /* Unused on A3XX */
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unsigned int size; /* Size of surface used to store GMEM */
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unsigned int width; /* Width of surface used to store GMEM */
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unsigned int height; /* Height of surface used to store GMEM */
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unsigned int pitch; /* Pitch of surface used to store GMEM */
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unsigned int gmem_pitch; /* Pitch value used for GMEM */
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unsigned int *gmem_save_commands; /* Unused on A3XX */
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unsigned int *gmem_restore_commands; /* Unused on A3XX */
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unsigned int gmem_save[3];
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unsigned int gmem_restore[3];
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struct kgsl_memdesc quad_vertices;
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struct kgsl_memdesc quad_texcoords;
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struct kgsl_memdesc quad_vertices_restore;
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};
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struct adreno_context {
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pid_t pid;
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char pid_name[TASK_COMM_LEN];
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unsigned int id;
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unsigned int ib_gpu_time_used;
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uint32_t flags;
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uint32_t pagefault;
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unsigned long pagefault_ts;
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unsigned int type;
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struct kgsl_pagetable *pagetable;
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struct kgsl_memdesc gpustate;
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unsigned int reg_restore[3];
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unsigned int shader_save[3];
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unsigned int shader_restore[3];
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/* Information of the GMEM shadow that is created in context create */
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struct gmem_shadow_t context_gmem_shadow;
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/* A2XX specific items */
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unsigned int reg_save[3];
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unsigned int shader_fixup[3];
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unsigned int chicken_restore[3];
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unsigned int bin_base_offset;
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/* A3XX specific items */
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unsigned int regconstant_save[3];
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unsigned int constant_restore[3];
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unsigned int hlsqcontrol_restore[3];
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unsigned int save_fixup[3];
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unsigned int restore_fixup[3];
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struct kgsl_memdesc shader_load_commands[2];
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struct kgsl_memdesc shader_save_commands[4];
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struct kgsl_memdesc constant_save_commands[3];
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struct kgsl_memdesc constant_load_commands[3];
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struct kgsl_memdesc cond_execs[4];
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struct kgsl_memdesc hlsqcontrol_restore_commands[1];
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struct kgsl_device_private *dev_priv;
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};
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int adreno_drawctxt_create(struct kgsl_device *device,
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struct kgsl_pagetable *pagetable,
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struct kgsl_context *context,
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uint32_t *flags);
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void adreno_drawctxt_destroy(struct kgsl_device *device,
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struct kgsl_context *context);
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void adreno_drawctxt_switch(struct adreno_device *adreno_dev,
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struct adreno_context *drawctxt,
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unsigned int flags);
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void adreno_drawctxt_set_bin_base_offset(struct kgsl_device *device,
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struct kgsl_context *context,
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unsigned int offset);
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/* GPU context switch helper functions */
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void build_quad_vtxbuff(struct adreno_context *drawctxt,
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struct gmem_shadow_t *shadow, unsigned int **incmd);
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unsigned int uint2float(unsigned int);
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static inline unsigned int virt2gpu(unsigned int *cmd,
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struct kgsl_memdesc *memdesc)
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{
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return memdesc->gpuaddr + ((char *) cmd - (char *) memdesc->hostptr);
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}
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static inline void create_ib1(struct adreno_context *drawctxt,
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unsigned int *cmd,
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unsigned int *start,
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unsigned int *end)
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{
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cmd[0] = CP_HDR_INDIRECT_BUFFER_PFD;
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cmd[1] = virt2gpu(start, &drawctxt->gpustate);
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cmd[2] = end - start;
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}
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static inline unsigned int *reg_range(unsigned int *cmd, unsigned int start,
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unsigned int end)
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{
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*cmd++ = CP_REG(start); /* h/w regs, start addr */
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*cmd++ = end - start + 1; /* count */
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return cmd;
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}
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static inline void calc_gmemsize(struct gmem_shadow_t *shadow, int gmem_size)
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{
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int w = 64, h = 64;
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shadow->format = COLORX_8_8_8_8;
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/* convert from bytes to 32-bit words */
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gmem_size = (gmem_size + 3) / 4;
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while ((w * h) < gmem_size) {
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if (w < h)
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w *= 2;
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else
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h *= 2;
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}
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shadow->pitch = shadow->width = w;
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shadow->height = h;
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shadow->gmem_pitch = shadow->pitch;
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shadow->size = shadow->pitch * shadow->height * 4;
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}
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#endif /* __ADRENO_DRAWCTXT_H */
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