575 lines
12 KiB
C
575 lines
12 KiB
C
/*
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* Driver for NEC VR4100 series General-purpose I/O Unit.
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*
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* Copyright (C) 2002 MontaVista Software Inc.
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* Author: Yoichi Yuasa <source@mvista.com>
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* Copyright (C) 2003-2009 Yoichi Yuasa <yuasa@linux-mips.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/errno.h>
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#include <linux/fs.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <asm/vr41xx/giu.h>
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#include <asm/vr41xx/irq.h>
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#include <asm/vr41xx/vr41xx.h>
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MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
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MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
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MODULE_LICENSE("GPL");
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#define GIUIOSELL 0x00
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#define GIUIOSELH 0x02
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#define GIUPIODL 0x04
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#define GIUPIODH 0x06
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#define GIUINTSTATL 0x08
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#define GIUINTSTATH 0x0a
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#define GIUINTENL 0x0c
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#define GIUINTENH 0x0e
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#define GIUINTTYPL 0x10
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#define GIUINTTYPH 0x12
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#define GIUINTALSELL 0x14
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#define GIUINTALSELH 0x16
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#define GIUINTHTSELL 0x18
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#define GIUINTHTSELH 0x1a
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#define GIUPODATL 0x1c
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#define GIUPODATEN 0x1c
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#define GIUPODATH 0x1e
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#define PIOEN0 0x0100
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#define PIOEN1 0x0200
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#define GIUPODAT 0x1e
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#define GIUFEDGEINHL 0x20
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#define GIUFEDGEINHH 0x22
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#define GIUREDGEINHL 0x24
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#define GIUREDGEINHH 0x26
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#define GIUUSEUPDN 0x1e0
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#define GIUTERMUPDN 0x1e2
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#define GPIO_HAS_PULLUPDOWN_IO 0x0001
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#define GPIO_HAS_OUTPUT_ENABLE 0x0002
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#define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
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enum {
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GPIO_INPUT,
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GPIO_OUTPUT,
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};
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static DEFINE_SPINLOCK(giu_lock);
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static unsigned long giu_flags;
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static void __iomem *giu_base;
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#define giu_read(offset) readw(giu_base + (offset))
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#define giu_write(offset, value) writew((value), giu_base + (offset))
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#define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
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#define GIUINT_HIGH_OFFSET 16
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#define GIUINT_HIGH_MAX 32
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static inline u16 giu_set(u16 offset, u16 set)
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{
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u16 data;
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data = giu_read(offset);
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data |= set;
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giu_write(offset, data);
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return data;
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}
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static inline u16 giu_clear(u16 offset, u16 clear)
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{
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u16 data;
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data = giu_read(offset);
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data &= ~clear;
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giu_write(offset, data);
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return data;
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}
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static void ack_giuint_low(struct irq_data *d)
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{
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giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(d->irq));
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}
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static void mask_giuint_low(struct irq_data *d)
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{
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giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
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}
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static void mask_ack_giuint_low(struct irq_data *d)
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{
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unsigned int pin;
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pin = GPIO_PIN_OF_IRQ(d->irq);
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giu_clear(GIUINTENL, 1 << pin);
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giu_write(GIUINTSTATL, 1 << pin);
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}
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static void unmask_giuint_low(struct irq_data *d)
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{
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giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
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}
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static struct irq_chip giuint_low_irq_chip = {
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.name = "GIUINTL",
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.irq_ack = ack_giuint_low,
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.irq_mask = mask_giuint_low,
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.irq_mask_ack = mask_ack_giuint_low,
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.irq_unmask = unmask_giuint_low,
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};
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static void ack_giuint_high(struct irq_data *d)
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{
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giu_write(GIUINTSTATH,
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1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
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}
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static void mask_giuint_high(struct irq_data *d)
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{
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giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
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}
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static void mask_ack_giuint_high(struct irq_data *d)
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{
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unsigned int pin;
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pin = GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET;
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giu_clear(GIUINTENH, 1 << pin);
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giu_write(GIUINTSTATH, 1 << pin);
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}
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static void unmask_giuint_high(struct irq_data *d)
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{
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giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
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}
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static struct irq_chip giuint_high_irq_chip = {
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.name = "GIUINTH",
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.irq_ack = ack_giuint_high,
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.irq_mask = mask_giuint_high,
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.irq_mask_ack = mask_ack_giuint_high,
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.irq_unmask = unmask_giuint_high,
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};
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static int giu_get_irq(unsigned int irq)
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{
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u16 pendl, pendh, maskl, maskh;
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int i;
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pendl = giu_read(GIUINTSTATL);
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pendh = giu_read(GIUINTSTATH);
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maskl = giu_read(GIUINTENL);
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maskh = giu_read(GIUINTENH);
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maskl &= pendl;
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maskh &= pendh;
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if (maskl) {
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for (i = 0; i < 16; i++) {
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if (maskl & (1 << i))
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return GIU_IRQ(i);
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}
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} else if (maskh) {
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for (i = 0; i < 16; i++) {
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if (maskh & (1 << i))
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return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
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}
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}
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printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
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maskl, pendl, maskh, pendh);
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atomic_inc(&irq_err_count);
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return -EINVAL;
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}
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void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
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irq_signal_t signal)
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{
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u16 mask;
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if (pin < GIUINT_HIGH_OFFSET) {
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mask = 1 << pin;
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if (trigger != IRQ_TRIGGER_LEVEL) {
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giu_set(GIUINTTYPL, mask);
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if (signal == IRQ_SIGNAL_HOLD)
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giu_set(GIUINTHTSELL, mask);
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else
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giu_clear(GIUINTHTSELL, mask);
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if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
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switch (trigger) {
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case IRQ_TRIGGER_EDGE_FALLING:
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giu_set(GIUFEDGEINHL, mask);
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giu_clear(GIUREDGEINHL, mask);
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break;
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case IRQ_TRIGGER_EDGE_RISING:
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giu_clear(GIUFEDGEINHL, mask);
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giu_set(GIUREDGEINHL, mask);
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break;
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default:
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giu_set(GIUFEDGEINHL, mask);
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giu_set(GIUREDGEINHL, mask);
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break;
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}
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}
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irq_set_chip_and_handler(GIU_IRQ(pin),
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&giuint_low_irq_chip,
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handle_edge_irq);
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} else {
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giu_clear(GIUINTTYPL, mask);
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giu_clear(GIUINTHTSELL, mask);
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irq_set_chip_and_handler(GIU_IRQ(pin),
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&giuint_low_irq_chip,
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handle_level_irq);
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}
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giu_write(GIUINTSTATL, mask);
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} else if (pin < GIUINT_HIGH_MAX) {
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mask = 1 << (pin - GIUINT_HIGH_OFFSET);
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if (trigger != IRQ_TRIGGER_LEVEL) {
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giu_set(GIUINTTYPH, mask);
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if (signal == IRQ_SIGNAL_HOLD)
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giu_set(GIUINTHTSELH, mask);
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else
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giu_clear(GIUINTHTSELH, mask);
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if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
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switch (trigger) {
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case IRQ_TRIGGER_EDGE_FALLING:
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giu_set(GIUFEDGEINHH, mask);
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giu_clear(GIUREDGEINHH, mask);
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break;
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case IRQ_TRIGGER_EDGE_RISING:
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giu_clear(GIUFEDGEINHH, mask);
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giu_set(GIUREDGEINHH, mask);
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break;
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default:
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giu_set(GIUFEDGEINHH, mask);
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giu_set(GIUREDGEINHH, mask);
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break;
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}
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}
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irq_set_chip_and_handler(GIU_IRQ(pin),
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&giuint_high_irq_chip,
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handle_edge_irq);
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} else {
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giu_clear(GIUINTTYPH, mask);
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giu_clear(GIUINTHTSELH, mask);
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irq_set_chip_and_handler(GIU_IRQ(pin),
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&giuint_high_irq_chip,
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handle_level_irq);
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}
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giu_write(GIUINTSTATH, mask);
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}
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}
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EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
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void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
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{
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u16 mask;
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if (pin < GIUINT_HIGH_OFFSET) {
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mask = 1 << pin;
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if (level == IRQ_LEVEL_HIGH)
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giu_set(GIUINTALSELL, mask);
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else
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giu_clear(GIUINTALSELL, mask);
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giu_write(GIUINTSTATL, mask);
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} else if (pin < GIUINT_HIGH_MAX) {
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mask = 1 << (pin - GIUINT_HIGH_OFFSET);
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if (level == IRQ_LEVEL_HIGH)
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giu_set(GIUINTALSELH, mask);
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else
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giu_clear(GIUINTALSELH, mask);
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giu_write(GIUINTSTATH, mask);
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}
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}
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EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
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static int giu_set_direction(struct gpio_chip *chip, unsigned pin, int dir)
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{
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u16 offset, mask, reg;
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unsigned long flags;
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if (pin >= chip->ngpio)
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return -EINVAL;
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if (pin < 16) {
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offset = GIUIOSELL;
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mask = 1 << pin;
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} else if (pin < 32) {
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offset = GIUIOSELH;
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mask = 1 << (pin - 16);
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} else {
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if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
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offset = GIUPODATEN;
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mask = 1 << (pin - 32);
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} else {
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switch (pin) {
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case 48:
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offset = GIUPODATH;
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mask = PIOEN0;
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break;
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case 49:
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offset = GIUPODATH;
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mask = PIOEN1;
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break;
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default:
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return -EINVAL;
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}
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}
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}
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spin_lock_irqsave(&giu_lock, flags);
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reg = giu_read(offset);
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if (dir == GPIO_OUTPUT)
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reg |= mask;
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else
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reg &= ~mask;
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giu_write(offset, reg);
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spin_unlock_irqrestore(&giu_lock, flags);
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return 0;
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}
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int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
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{
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u16 reg, mask;
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unsigned long flags;
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if ((giu_flags & GPIO_HAS_PULLUPDOWN_IO) != GPIO_HAS_PULLUPDOWN_IO)
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return -EPERM;
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if (pin >= 15)
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return -EINVAL;
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mask = 1 << pin;
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spin_lock_irqsave(&giu_lock, flags);
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if (pull == GPIO_PULL_UP || pull == GPIO_PULL_DOWN) {
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reg = giu_read(GIUTERMUPDN);
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if (pull == GPIO_PULL_UP)
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reg |= mask;
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else
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reg &= ~mask;
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giu_write(GIUTERMUPDN, reg);
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reg = giu_read(GIUUSEUPDN);
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reg |= mask;
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giu_write(GIUUSEUPDN, reg);
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} else {
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reg = giu_read(GIUUSEUPDN);
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reg &= ~mask;
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giu_write(GIUUSEUPDN, reg);
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}
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spin_unlock_irqrestore(&giu_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown);
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static int vr41xx_gpio_get(struct gpio_chip *chip, unsigned pin)
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{
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u16 reg, mask;
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if (pin >= chip->ngpio)
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return -EINVAL;
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if (pin < 16) {
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reg = giu_read(GIUPIODL);
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mask = 1 << pin;
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} else if (pin < 32) {
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reg = giu_read(GIUPIODH);
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mask = 1 << (pin - 16);
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} else if (pin < 48) {
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reg = giu_read(GIUPODATL);
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mask = 1 << (pin - 32);
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} else {
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reg = giu_read(GIUPODATH);
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mask = 1 << (pin - 48);
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}
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if (reg & mask)
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return 1;
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return 0;
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}
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static void vr41xx_gpio_set(struct gpio_chip *chip, unsigned pin,
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int value)
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{
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u16 offset, mask, reg;
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unsigned long flags;
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if (pin >= chip->ngpio)
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return;
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if (pin < 16) {
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offset = GIUPIODL;
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mask = 1 << pin;
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} else if (pin < 32) {
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offset = GIUPIODH;
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mask = 1 << (pin - 16);
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} else if (pin < 48) {
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offset = GIUPODATL;
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mask = 1 << (pin - 32);
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} else {
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offset = GIUPODATH;
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mask = 1 << (pin - 48);
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}
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spin_lock_irqsave(&giu_lock, flags);
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reg = giu_read(offset);
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if (value)
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reg |= mask;
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else
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reg &= ~mask;
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giu_write(offset, reg);
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spin_unlock_irqrestore(&giu_lock, flags);
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}
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static int vr41xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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return giu_set_direction(chip, offset, GPIO_INPUT);
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}
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static int vr41xx_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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vr41xx_gpio_set(chip, offset, value);
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return giu_set_direction(chip, offset, GPIO_OUTPUT);
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}
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static int vr41xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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if (offset >= chip->ngpio)
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return -EINVAL;
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return GIU_IRQ_BASE + offset;
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}
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static struct gpio_chip vr41xx_gpio_chip = {
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.label = "vr41xx",
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.owner = THIS_MODULE,
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.direction_input = vr41xx_gpio_direction_input,
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.get = vr41xx_gpio_get,
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.direction_output = vr41xx_gpio_direction_output,
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.set = vr41xx_gpio_set,
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.to_irq = vr41xx_gpio_to_irq,
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};
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static int __devinit giu_probe(struct platform_device *pdev)
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{
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struct resource *res;
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unsigned int trigger, i, pin;
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struct irq_chip *chip;
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int irq, retval;
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switch (pdev->id) {
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case GPIO_50PINS_PULLUPDOWN:
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giu_flags = GPIO_HAS_PULLUPDOWN_IO;
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vr41xx_gpio_chip.ngpio = 50;
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break;
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case GPIO_36PINS:
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vr41xx_gpio_chip.ngpio = 36;
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break;
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case GPIO_48PINS_EDGE_SELECT:
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giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
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vr41xx_gpio_chip.ngpio = 48;
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break;
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default:
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dev_err(&pdev->dev, "GIU: unknown ID %d\n", pdev->id);
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return -ENODEV;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -EBUSY;
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giu_base = ioremap(res->start, resource_size(res));
|
|
if (!giu_base)
|
|
return -ENOMEM;
|
|
|
|
vr41xx_gpio_chip.dev = &pdev->dev;
|
|
|
|
retval = gpiochip_add(&vr41xx_gpio_chip);
|
|
|
|
giu_write(GIUINTENL, 0);
|
|
giu_write(GIUINTENH, 0);
|
|
|
|
trigger = giu_read(GIUINTTYPH) << 16;
|
|
trigger |= giu_read(GIUINTTYPL);
|
|
for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
|
|
pin = GPIO_PIN_OF_IRQ(i);
|
|
if (pin < GIUINT_HIGH_OFFSET)
|
|
chip = &giuint_low_irq_chip;
|
|
else
|
|
chip = &giuint_high_irq_chip;
|
|
|
|
if (trigger & (1 << pin))
|
|
irq_set_chip_and_handler(i, chip, handle_edge_irq);
|
|
else
|
|
irq_set_chip_and_handler(i, chip, handle_level_irq);
|
|
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0 || irq >= nr_irqs)
|
|
return -EBUSY;
|
|
|
|
return cascade_irq(irq, giu_get_irq);
|
|
}
|
|
|
|
static int __devexit giu_remove(struct platform_device *pdev)
|
|
{
|
|
if (giu_base) {
|
|
iounmap(giu_base);
|
|
giu_base = NULL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver giu_device_driver = {
|
|
.probe = giu_probe,
|
|
.remove = __devexit_p(giu_remove),
|
|
.driver = {
|
|
.name = "GIU",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(giu_device_driver);
|