197 lines
5.9 KiB
C
197 lines
5.9 KiB
C
/**
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* AMCC SoC PPC4xx Crypto Driver
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*
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* Copyright (c) 2008 Applied Micro Circuits Corporation.
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* All rights reserved. James Hsiao <jhsiao@amcc.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This is the header file for AMCC Crypto offload Linux device driver for
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* use with Linux CryptoAPI.
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*/
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#ifndef __CRYPTO4XX_CORE_H__
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#define __CRYPTO4XX_CORE_H__
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#include <crypto/internal/hash.h>
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#define PPC460SX_SDR0_SRST 0x201
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#define PPC405EX_SDR0_SRST 0x200
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#define PPC460EX_SDR0_SRST 0x201
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#define PPC460EX_CE_RESET 0x08000000
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#define PPC460SX_CE_RESET 0x20000000
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#define PPC405EX_CE_RESET 0x00000008
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#define CRYPTO4XX_CRYPTO_PRIORITY 300
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#define PPC4XX_LAST_PD 63
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#define PPC4XX_NUM_PD 64
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#define PPC4XX_LAST_GD 1023
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#define PPC4XX_NUM_GD 1024
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#define PPC4XX_LAST_SD 63
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#define PPC4XX_NUM_SD 64
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#define PPC4XX_SD_BUFFER_SIZE 2048
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#define PD_ENTRY_INUSE 1
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#define PD_ENTRY_FREE 0
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#define ERING_WAS_FULL 0xffffffff
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struct crypto4xx_device;
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struct pd_uinfo {
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struct crypto4xx_device *dev;
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u32 state;
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u32 using_sd;
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u32 first_gd; /* first gather discriptor
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used by this packet */
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u32 num_gd; /* number of gather discriptor
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used by this packet */
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u32 first_sd; /* first scatter discriptor
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used by this packet */
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u32 num_sd; /* number of scatter discriptors
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used by this packet */
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void *sa_va; /* shadow sa, when using cp from ctx->sa */
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u32 sa_pa;
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void *sr_va; /* state record for shadow sa */
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u32 sr_pa;
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struct scatterlist *dest_va;
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struct crypto_async_request *async_req; /* base crypto request
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for this packet */
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};
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struct crypto4xx_device {
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struct crypto4xx_core_device *core_dev;
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char *name;
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u64 ce_phy_address;
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void __iomem *ce_base;
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void *pdr; /* base address of packet
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descriptor ring */
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dma_addr_t pdr_pa; /* physical address used to
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program ce pdr_base_register */
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void *gdr; /* gather descriptor ring */
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dma_addr_t gdr_pa; /* physical address used to
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program ce gdr_base_register */
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void *sdr; /* scatter descriptor ring */
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dma_addr_t sdr_pa; /* physical address used to
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program ce sdr_base_register */
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void *scatter_buffer_va;
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dma_addr_t scatter_buffer_pa;
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u32 scatter_buffer_size;
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void *shadow_sa_pool; /* pool of memory for sa in pd_uinfo */
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dma_addr_t shadow_sa_pool_pa;
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void *shadow_sr_pool; /* pool of memory for sr in pd_uinfo */
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dma_addr_t shadow_sr_pool_pa;
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u32 pdr_tail;
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u32 pdr_head;
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u32 gdr_tail;
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u32 gdr_head;
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u32 sdr_tail;
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u32 sdr_head;
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void *pdr_uinfo;
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struct list_head alg_list; /* List of algorithm supported
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by this device */
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};
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struct crypto4xx_core_device {
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struct device *device;
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struct platform_device *ofdev;
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struct crypto4xx_device *dev;
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u32 int_status;
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u32 irq;
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struct tasklet_struct tasklet;
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spinlock_t lock;
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};
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struct crypto4xx_ctx {
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struct crypto4xx_device *dev;
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void *sa_in;
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dma_addr_t sa_in_dma_addr;
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void *sa_out;
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dma_addr_t sa_out_dma_addr;
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void *state_record;
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dma_addr_t state_record_dma_addr;
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u32 sa_len;
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u32 offset_to_sr_ptr; /* offset to state ptr, in dynamic sa */
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u32 direction;
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u32 next_hdr;
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u32 save_iv;
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u32 pd_ctl_len;
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u32 pd_ctl;
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u32 bypass;
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u32 is_hash;
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u32 hash_final;
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};
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struct crypto4xx_req_ctx {
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struct crypto4xx_device *dev; /* Device in which
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operation to send to */
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void *sa;
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u32 sa_dma_addr;
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u16 sa_len;
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};
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struct crypto4xx_alg_common {
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u32 type;
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union {
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struct crypto_alg cipher;
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struct ahash_alg hash;
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} u;
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};
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struct crypto4xx_alg {
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struct list_head entry;
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struct crypto4xx_alg_common alg;
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struct crypto4xx_device *dev;
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};
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static inline struct crypto4xx_alg *crypto_alg_to_crypto4xx_alg(
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struct crypto_alg *x)
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{
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switch (x->cra_flags & CRYPTO_ALG_TYPE_MASK) {
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case CRYPTO_ALG_TYPE_AHASH:
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return container_of(__crypto_ahash_alg(x),
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struct crypto4xx_alg, alg.u.hash);
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}
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return container_of(x, struct crypto4xx_alg, alg.u.cipher);
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}
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extern int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size);
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extern void crypto4xx_free_sa(struct crypto4xx_ctx *ctx);
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extern u32 crypto4xx_alloc_sa_rctx(struct crypto4xx_ctx *ctx,
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struct crypto4xx_ctx *rctx);
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extern void crypto4xx_free_sa_rctx(struct crypto4xx_ctx *rctx);
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extern void crypto4xx_free_ctx(struct crypto4xx_ctx *ctx);
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extern u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx);
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extern u32 get_dynamic_sa_offset_state_ptr_field(struct crypto4xx_ctx *ctx);
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extern u32 get_dynamic_sa_offset_key_field(struct crypto4xx_ctx *ctx);
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extern u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx);
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extern void crypto4xx_memcpy_le(unsigned int *dst,
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const unsigned char *buf, int len);
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extern u32 crypto4xx_build_pd(struct crypto_async_request *req,
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struct crypto4xx_ctx *ctx,
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struct scatterlist *src,
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struct scatterlist *dst,
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unsigned int datalen,
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void *iv, u32 iv_len);
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extern int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher,
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const u8 *key, unsigned int keylen);
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extern int crypto4xx_encrypt(struct ablkcipher_request *req);
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extern int crypto4xx_decrypt(struct ablkcipher_request *req);
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extern int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm);
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extern int crypto4xx_hash_digest(struct ahash_request *req);
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extern int crypto4xx_hash_final(struct ahash_request *req);
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extern int crypto4xx_hash_update(struct ahash_request *req);
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extern int crypto4xx_hash_init(struct ahash_request *req);
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#endif
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