752 lines
15 KiB
C
752 lines
15 KiB
C
/* Copyright (c) 2010, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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perf-smp.c
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DESCRIPTION
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Manipulation, initialization of the ARMV7 Performance counter register.
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EXTERNALIZED FUNCTIONS
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INITIALIZATION AND SEQUENCING REQUIREMENTS
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*/
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/*
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INCLUDE FILES FOR MODULE
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*/
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/time.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include "l2_cp15_registers.h"
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/*
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DEFINITIONS AND DECLARATIONS FOR MODULE
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This section contains definitions for constants, macros, types, variables
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and other items needed by this module.
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*/
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/*
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Constant / Define Declarations
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*/
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#define PM_NUM_COUNTERS 4
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#define L2_PM_ERR -1
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/*------------------------------------------------------------------------
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* Global control bits
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------------------------------------------------------------------------*/
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#define PM_L2_GLOBAL_ENABLE (1<<0)
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#define PM_L2_EVENT_RESET (1<<1)
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#define PM_L2_CYCLE_RESET (1<<2)
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#define PM_L2_CLKDIV (1<<3)
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#define PM_L2_GLOBAL_TRACE (1<<4)
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#define PM_L2_DISABLE_PROHIBIT (1<<5)
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/*---------------------------------------------------------------------------
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* Enable and clear bits for each event/trigger
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----------------------------------------------------------------------------*/
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#define PM_L2EV0_ENABLE (1<<0)
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#define PM_L2EV1_ENABLE (1<<1)
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#define PM_L2EV2_ENABLE (1<<2)
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#define PM_L2EV3_ENABLE (1<<3)
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#define PM_L2_COUNT_ENABLE (1<<31)
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#define PM_L2_ALL_ENABLE (0x8000000F)
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/*-----------------------------------------------------------------------------
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* Overflow actions
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------------------------------------------------------------------------------*/
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#define PM_L2_OVERFLOW_NOACTION (0)
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#define PM_L2_OVERFLOW_HALT (1)
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#define PM_L2_OVERFLOW_STOP (2)
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#define PM_L2_OVERFLOW_SKIP (3)
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/*
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* Shifts for each trigger type
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*/
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#define PM_STOP_SHIFT 24
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#define PM_RELOAD_SHIFT 22
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#define PM_RESUME_SHIFT 20
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#define PM_SUSPEND_SHIFT 18
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#define PM_START_SHIFT 16
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#define PM_STOPALL_SHIFT 15
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#define PM_STOPCOND_SHIFT 12
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#define PM_RELOADCOND_SHIFT 9
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#define PM_RESUMECOND_SHIFT 6
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#define PM_SUSPENDCOND_SHIFT 3
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#define PM_STARTCOND_SHIFT 0
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/*---------------------------------------------------------------------------
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External control register. What todo when various events happen.
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Triggering events, etc.
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----------------------------------------------------------------------------*/
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#define PM_EXTTR0 0
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#define PM_EXTTR1 1
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#define PM_EXTTR2 2
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#define PM_EXTTR3 3
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#define PM_COND_NO_STOP 0
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#define PM_COND_STOP_CNTOVRFLW 1
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#define PM_COND_STOP_EXTERNAL 4
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#define PM_COND_STOP_TRACE 5
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#define PM_COND_STOP_EVOVRFLW 6
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#define PM_COND_STOP_EVTYPER 7
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/*--------------------------------------------------------------------------
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Protect against concurrent access. There is an index register that is
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used to select the appropriate bank of registers. If multiple processes
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are writting this at different times we could have a mess...
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---------------------------------------------------------------------------*/
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#define PM_LOCK()
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#define PM_UNLOCK()
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#define PRINT printk
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/*--------------------------------------------------------------------------
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The Event definitions
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--------------------------------------------------------------------------*/
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#define L2PM_EVT_PM0_EVT0 0x00
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#define L2PM_EVT_PM0_EVT1 0x01
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#define L2PM_EVT_PM0_EVT2 0x02
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#define L2PM_EVT_PM0_EVT3 0x03
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#define L2PM_EVT_PM1_EVT0 0x04
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#define L2PM_EVT_PM1_EVT1 0x05
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#define L2PM_EVT_PM1_EVT2 0x06
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#define L2PM_EVT_PM1_EVT3 0x07
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#define L2PM_EVT_PM2_EVT0 0x08
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#define L2PM_EVT_PM2_EVT1 0x09
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#define L2PM_EVT_PM2_EVT2 0x0a
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#define L2PM_EVT_PM2_EVT3 0x0b
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#define L2PM_EVT_PM3_EVT0 0x0c
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#define L2PM_EVT_PM3_EVT1 0x0d
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#define L2PM_EVT_PM3_EVT2 0x0e
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#define L2PM_EVT_PM3_EVT3 0x0f
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#define L2PM_EVT_PM4_EVT0 0x10
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#define L2PM_EVT_PM4_EVT1 0x11
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#define L2PM_EVT_PM4_EVT2 0x12
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#define L2PM_EVT_PM4_EVT3 0x13
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/*
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Type Declarations
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*/
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/*
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Local Object Definitions
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*/
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unsigned long l2_pm_cycle_overflow_count;
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unsigned long l2_pm_overflow_count[PM_NUM_COUNTERS];
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/*---------------------------------------------------------------------------
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Max number of events read from the config registers
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---------------------------------------------------------------------------*/
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static int pm_l2_max_events;
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static int irqid;
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/*
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Function Definitions
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*/
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/*
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FUNCTION l2_pm_group_stop
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DESCRIPTION Stop a group of the performance monitors. Event monitor 0 is bit
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0, event monitor 1 bit 1, etc. The cycle count can also be disable with
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bit 31. Macros are provided for all of the indexes including an ALL.
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DEPENDENCIES
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RETURN VALUE
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None
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SIDE EFFECTS
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Stops the performance monitoring for the index passed.
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*/
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void pm_l2_group_stop(unsigned long mask)
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{
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WCP15_L2PMCNTENCLR(mask);
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}
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/*
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FUNCTION l2_pm_group_start
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DESCRIPTION Start a group of the performance monitors. Event monitor 0 is bit
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0, event monitor 1 bit 1, etc. The cycle count can also be enabled with
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bit 31. Macros are provided for all of the indexes including an ALL.
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DEPENDENCIES
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RETURN VALUE
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None
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SIDE EFFECTS
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Starts the performance monitoring for the index passed.
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*/
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void pm_l2_group_start(unsigned long mask)
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{
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WCP15_L2PMCNTENSET(mask);
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}
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/*
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FUNCTION l2_pm_get_overflow
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DESCRIPTION Return the overflow condition for the index passed.
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DEPENDENCIES
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RETURN VALUE
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0 no overflow
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!0 (anything else) overflow;
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SIDE EFFECTS
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*/
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unsigned long l2_pm_get_overflow(int index)
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{
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unsigned long overflow = 0;
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/*
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* Range check
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*/
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if (index > pm_l2_max_events)
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return L2_PM_ERR;
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RCP15_L2PMOVSR(overflow);
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return overflow & (1<<index);
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}
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/*
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FUNCTION l2_pm_get_cycle_overflow
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DESCRIPTION
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Returns if the cycle counter has overflowed or not.
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DEPENDENCIES
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RETURN VALUE
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0 no overflow
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!0 (anything else) overflow;
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SIDE EFFECTS
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*/
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unsigned long l2_pm_get_cycle_overflow(void)
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{
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unsigned long overflow = 0;
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RCP15_L2PMOVSR(overflow);
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return overflow & PM_L2_COUNT_ENABLE;
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}
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/*
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FUNCTION l2_pm_reset_overflow
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DESCRIPTION Reset the cycle counter overflow bit.
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DEPENDENCIES
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RETURN VALUE
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None
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SIDE EFFECTS
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*/
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void l2_pm_reset_overflow(int index)
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{
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WCP15_L2PMOVSR(1<<index);
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}
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/*
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FUNCTION l2_pm_reset_cycle_overflow
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DESCRIPTION Reset the cycle counter overflow bit.
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DEPENDENCIES
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RETURN VALUE
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None
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SIDE EFFECTS
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*/
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void l2_pm_reset_cycle_overflow(void)
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{
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WCP15_L2PMOVSR(PM_L2_COUNT_ENABLE);
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}
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/*
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FUNCTION l2_pm_get_cycle_count
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DESCRIPTION return the count in the cycle count register.
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DEPENDENCIES
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RETURN VALUE
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The value in the cycle count register.
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SIDE EFFECTS
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*/
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unsigned long l2_pm_get_cycle_count(void)
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{
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unsigned long cnt = 0;
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RCP15_L2PMCCNTR(cnt);
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return cnt;
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}
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/*
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FUNCTION l2_pm_reset_cycle_count
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DESCRIPTION reset the value in the cycle count register
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DEPENDENCIES
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RETURN VALUE
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NONE
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SIDE EFFECTS
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Resets the performance monitor cycle count register.
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Any interrupts period based on this overflow will be changed
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*/
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void l2_pm_reset_cycle_count(void)
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{
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WCP15_L2PMCNTENCLR(PM_L2_COUNT_ENABLE);
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}
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/*
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FUNCTION l2_pm_cycle_div_64
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DESCRIPTION Set the cycle counter to count every 64th cycle instead of
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every cycle when the value passed is 1, otherwise counts every cycle.
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DEPENDENCIES
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RETURN VALUE
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none
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SIDE EFFECTS
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Changes the rate at which cycles are counted. Anything that is reading
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the cycle count (pmGetCyucleCount) may get different results.
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*/
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void l2_pm_cycle_div_64(int enable)
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{
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unsigned long enables = 0;
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RCP15_L2PMCR(enables);
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if (enable)
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WCP15_L2PMCR(enables | PM_L2_CLKDIV);
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else
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WCP15_L2PMCR(enables & ~PM_L2_CLKDIV);
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}
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/*
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FUNCTION l2_pm_enable_cycle_counter
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DESCRIPTION Enable the cycle counter. Sets the bit in the enable register
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so the performance monitor counter starts up counting.
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DEPENDENCIES
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RETURN VALUE
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none
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SIDE EFFECTS
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*/
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void l2_pm_enable_cycle_counter(void)
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{
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/*
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* Enable the counter.
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*/
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WCP15_L2PMCNTENSET(PM_L2_COUNT_ENABLE);
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}
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/*
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FUNCTION l2_pm_disable_counter
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DESCRIPTION Disable a single counter based on the index passed.
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DEPENDENCIES
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RETURN VALUE
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none
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SIDE EFFECTS
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Any triggers that are based on the stoped counter may not trigger...
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*/
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void l2_pm_disable_counter(int index)
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{
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/*
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* Range check
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*/
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if (index > pm_l2_max_events)
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return;
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WCP15_L2PMCNTENCLR(1<<index);
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}
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/*
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FUNCTION l2_pm_enable_counter
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DESCRIPTION Enable the counter with the index passed.
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DEPENDENCIES
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RETURN VALUE
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none.
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SIDE EFFECTS
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*/
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void l2_pm_enable_counter(int index)
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{
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/*
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* Range check
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*/
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if (index > pm_l2_max_events)
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return;
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WCP15_L2PMCNTENSET(1<<index);
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}
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/*
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FUNCTION l2_pm_set_count
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DESCRIPTION Set the number of events in a register, used for resets
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passed.
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DEPENDENCIES
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RETURN VALUE
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-1 if the index is out of range
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SIDE EFFECTS
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*/
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int l2_pm_set_count(int index, unsigned long new_value)
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{
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unsigned long reg = 0;
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/*
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* Range check
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*/
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if (index > pm_l2_max_events)
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return L2_PM_ERR;
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/*
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* Lock, select the index and read the count...unlock
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*/
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PM_LOCK();
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WCP15_L2PMSELR(index);
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WCP15_L2PMXEVCNTR(new_value);
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PM_UNLOCK();
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return reg;
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}
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int l2_pm_reset_count(int index)
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{
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return l2_pm_set_count(index, 0);
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}
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/*
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FUNCTION l2_pm_get_count
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DESCRIPTION Return the number of events that have happened for the index
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passed.
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DEPENDENCIES
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RETURN VALUE
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-1 if the index is out of range
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The number of events if inrange
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SIDE EFFECTS
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*/
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unsigned long l2_pm_get_count(int index)
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{
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unsigned long reg = 0;
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/*
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* Range check
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*/
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if (index > pm_l2_max_events)
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return L2_PM_ERR;
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/*
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* Lock, select the index and read the count...unlock
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*/
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PM_LOCK();
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WCP15_L2PMSELR(index);
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RCP15_L2PMXEVCNTR(reg);
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PM_UNLOCK();
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return reg;
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}
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unsigned long get_filter_code(unsigned long event)
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{
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if (event == 0x0 || event == 0x4 || event == 0x08
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|| event == 0x0c || event == 0x10)
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return 0x0001003f;
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else if (event == 0x1 || event == 0x5 || event == 0x09
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|| event == 0x0d || event == 0x11)
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return 0x0002003f;
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else if (event == 0x2 || event == 0x6 || event == 0x0a
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|| event == 0x0e || event == 0x12)
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return 0x0004003f;
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else if (event == 0x3 || event == 0x7 || event == 0x0b
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|| event == 0x0f || event == 0x13)
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return 0x0008003f;
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else
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return 0;
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}
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int l2_pm_set_event(int index, unsigned long event)
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{
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unsigned long reg = 0;
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/*
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* Range check
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*/
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if (index > pm_l2_max_events)
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return L2_PM_ERR;
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/*
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* Lock, select the index and read the count...unlock
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*/
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PM_LOCK();
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WCP15_L2PMSELR(index);
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WCP15_L2PMXEVTYPER(event);
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/* WCP15_L2PMXEVFILTER(get_filter_code(event)); */
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WCP15_L2PMXEVFILTER(0x000f003f);
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PM_UNLOCK();
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return reg;
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}
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/*
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FUNCTION pm_set_local_bu
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DESCRIPTION Set the local BU triggers. Note that the MSB determines if
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these are enabled or not.
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DEPENDENCIES
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RETURN VALUE
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NONE
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SIDE EFFECTS
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*/
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void pm_set_local_bu(unsigned long value)
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{
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WCP15_L2PMEVTYPER0(value);
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}
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/*
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FUNCTION pm_set_local_cb
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DESCRIPTION Set the local CB triggers. Note that the MSB determines if
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these are enabled or not.
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DEPENDENCIES
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RETURN VALUE
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NONE
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SIDE EFFECTS
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*/
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void pm_set_local_cb(unsigned long value)
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{
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WCP15_L2PMEVTYPER1(value);
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}
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/*
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FUNCTION pm_set_local_mp
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DESCRIPTION Set the local MP triggers. Note that the MSB determines if
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these are enabled or not.
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DEPENDENCIES
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RETURN VALUE
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NONE
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SIDE EFFECTS
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*/
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void pm_set_local_mp(unsigned long value)
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{
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WCP15_L2PMEVTYPER2(value);
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}
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/*
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FUNCTION pm_set_local_sp
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DESCRIPTION Set the local SP triggers. Note that the MSB determines if
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these are enabled or not.
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DEPENDENCIES
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RETURN VALUE
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NONE
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SIDE EFFECTS
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*/
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void pm_set_local_sp(unsigned long value)
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{
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WCP15_L2PMEVTYPER3(value);
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}
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/*
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FUNCTION pm_set_local_scu
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DESCRIPTION Set the local SCU triggers. Note that the MSB determines if
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these are enabled or not.
|
|
|
|
DEPENDENCIES
|
|
|
|
RETURN VALUE
|
|
NONE
|
|
|
|
SIDE EFFECTS
|
|
*/
|
|
void pm_set_local_scu(unsigned long value)
|
|
{
|
|
WCP15_L2PMEVTYPER4(value);
|
|
}
|
|
|
|
/*
|
|
FUNCTION l2_pm_isr
|
|
|
|
DESCRIPTION:
|
|
Performance Monitor interrupt service routine to capture overflows
|
|
|
|
DEPENDENCIES
|
|
|
|
RETURN VALUE
|
|
|
|
SIDE EFFECTS
|
|
*/
|
|
static irqreturn_t l2_pm_isr(int irq, void *d)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < PM_NUM_COUNTERS; i++) {
|
|
if (l2_pm_get_overflow(i)) {
|
|
l2_pm_overflow_count[i]++;
|
|
l2_pm_reset_overflow(i);
|
|
}
|
|
}
|
|
|
|
if (l2_pm_get_cycle_overflow()) {
|
|
l2_pm_cycle_overflow_count++;
|
|
l2_pm_reset_cycle_overflow();
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
|
|
void l2_pm_stop_all(void)
|
|
{
|
|
WCP15_L2PMCNTENCLR(0xFFFFFFFF);
|
|
}
|
|
|
|
void l2_pm_reset_all(void)
|
|
{
|
|
WCP15_L2PMCR(0xF);
|
|
WCP15_L2PMOVSR(PM_L2_ALL_ENABLE); /* overflow clear */
|
|
}
|
|
|
|
void l2_pm_start_all(void)
|
|
{
|
|
WCP15_L2PMCNTENSET(PM_L2_ALL_ENABLE);
|
|
}
|
|
|
|
/*
|
|
FUNCTION l2_pm_initialize
|
|
|
|
DESCRIPTION Initialize the performanca monitoring for the v7 processor.
|
|
Ensures the cycle count is running and the event counters are enabled.
|
|
|
|
DEPENDENCIES
|
|
|
|
RETURN VALUE
|
|
NONE
|
|
|
|
SIDE EFFECTS
|
|
*/
|
|
void l2_pm_initialize(void)
|
|
{
|
|
unsigned long reg = 0;
|
|
unsigned char imp;
|
|
unsigned char id;
|
|
unsigned char num;
|
|
unsigned long enables = 0;
|
|
static int initialized;
|
|
|
|
if (initialized)
|
|
return;
|
|
initialized = 1;
|
|
|
|
irqid = SC_SICL2PERFMONIRPTREQ;
|
|
RCP15_L2PMCR(reg);
|
|
imp = (reg>>24) & 0xFF;
|
|
id = (reg>>16) & 0xFF;
|
|
pm_l2_max_events = num = (reg>>11) & 0xFF;
|
|
PRINT("V7 MP L2SCU Performance Monitor Capabilities\n");
|
|
PRINT(" Implementor %c(%d)\n", imp, imp);
|
|
PRINT(" Id %d %x\n", id, id);
|
|
PRINT(" Num Events %d %x\n", num, num);
|
|
PRINT("\nCycle counter enabled by default...\n");
|
|
|
|
/*
|
|
* Global enable, ensure the global enable is set so all
|
|
* subsequent actions take effect. Also resets the counts
|
|
*/
|
|
RCP15_L2PMCR(enables);
|
|
WCP15_L2PMCR(enables | PM_L2_GLOBAL_ENABLE | PM_L2_EVENT_RESET |
|
|
PM_L2_CYCLE_RESET | PM_L2_CLKDIV);
|
|
|
|
/*
|
|
* Enable access from user space
|
|
*/
|
|
|
|
/*
|
|
* Install interrupt handler and the enable the interrupts
|
|
*/
|
|
l2_pm_reset_cycle_overflow();
|
|
l2_pm_reset_overflow(0);
|
|
l2_pm_reset_overflow(1);
|
|
l2_pm_reset_overflow(2);
|
|
l2_pm_reset_overflow(3);
|
|
l2_pm_reset_overflow(4);
|
|
|
|
if (0 != request_irq(irqid, l2_pm_isr, 0, "l2perfmon", 0))
|
|
printk(KERN_ERR "%s:%d request_irq returned error\n",
|
|
__FILE__, __LINE__);
|
|
WCP15_L2PMINTENSET(PM_L2_ALL_ENABLE);
|
|
/*
|
|
* Enable the cycle counter. Default, count 1:1 no divisor.
|
|
*/
|
|
l2_pm_enable_cycle_counter();
|
|
|
|
}
|
|
|
|
void l2_pm_free_irq(void)
|
|
{
|
|
free_irq(irqid, 0);
|
|
}
|
|
|
|
void l2_pm_deinitialize(void)
|
|
{
|
|
unsigned long enables = 0;
|
|
RCP15_L2PMCR(enables);
|
|
WCP15_L2PMCR(enables & ~PM_L2_GLOBAL_ENABLE);
|
|
}
|
|
|