165 lines
5.2 KiB
C
165 lines
5.2 KiB
C
/*
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* arch/arm/mach-spear3xx/include/mach/misc_regs.h
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*
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* Miscellaneous registers definitions for SPEAr3xx machine family
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __MACH_MISC_REGS_H
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#define __MACH_MISC_REGS_H
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#include <mach/hardware.h>
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#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
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#define SOC_CFG_CTR (MISC_BASE + 0x000)
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#define DIAG_CFG_CTR (MISC_BASE + 0x004)
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#define PLL1_CTR (MISC_BASE + 0x008)
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#define PLL1_FRQ (MISC_BASE + 0x00C)
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#define PLL1_MOD (MISC_BASE + 0x010)
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#define PLL2_CTR (MISC_BASE + 0x014)
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/* PLL_CTR register masks */
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#define PLL_ENABLE 2
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#define PLL_MODE_SHIFT 4
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#define PLL_MODE_MASK 0x3
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#define PLL_MODE_NORMAL 0
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#define PLL_MODE_FRACTION 1
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#define PLL_MODE_DITH_DSB 2
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#define PLL_MODE_DITH_SSB 3
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#define PLL2_FRQ (MISC_BASE + 0x018)
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/* PLL FRQ register masks */
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#define PLL_DIV_N_SHIFT 0
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#define PLL_DIV_N_MASK 0xFF
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#define PLL_DIV_P_SHIFT 8
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#define PLL_DIV_P_MASK 0x7
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#define PLL_NORM_FDBK_M_SHIFT 24
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#define PLL_NORM_FDBK_M_MASK 0xFF
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#define PLL_DITH_FDBK_M_SHIFT 16
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#define PLL_DITH_FDBK_M_MASK 0xFFFF
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#define PLL2_MOD (MISC_BASE + 0x01C)
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#define PLL_CLK_CFG (MISC_BASE + 0x020)
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#define CORE_CLK_CFG (MISC_BASE + 0x024)
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/* CORE CLK CFG register masks */
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#define PLL_HCLK_RATIO_SHIFT 10
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#define PLL_HCLK_RATIO_MASK 0x3
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#define HCLK_PCLK_RATIO_SHIFT 8
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#define HCLK_PCLK_RATIO_MASK 0x3
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#define PERIP_CLK_CFG (MISC_BASE + 0x028)
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/* PERIP_CLK_CFG register masks */
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#define UART_CLK_SHIFT 4
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#define UART_CLK_MASK 0x1
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#define FIRDA_CLK_SHIFT 5
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#define FIRDA_CLK_MASK 0x3
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#define GPT0_CLK_SHIFT 8
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#define GPT1_CLK_SHIFT 11
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#define GPT2_CLK_SHIFT 12
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#define GPT_CLK_MASK 0x1
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#define AUX_CLK_PLL3_VAL 0
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#define AUX_CLK_PLL1_VAL 1
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#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
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/* PERIP1_CLK_ENB register masks */
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#define UART_CLK_ENB 3
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#define SSP_CLK_ENB 5
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#define I2C_CLK_ENB 7
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#define JPEG_CLK_ENB 8
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#define FIRDA_CLK_ENB 10
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#define GPT1_CLK_ENB 11
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#define GPT2_CLK_ENB 12
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#define ADC_CLK_ENB 15
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#define RTC_CLK_ENB 17
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#define GPIO_CLK_ENB 18
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#define DMA_CLK_ENB 19
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#define SMI_CLK_ENB 21
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#define GMAC_CLK_ENB 23
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#define USBD_CLK_ENB 24
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#define USBH_CLK_ENB 25
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#define C3_CLK_ENB 31
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#define SOC_CORE_ID (MISC_BASE + 0x030)
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#define RAS_CLK_ENB (MISC_BASE + 0x034)
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#define PERIP1_SOF_RST (MISC_BASE + 0x038)
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/* PERIP1_SOF_RST register masks */
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#define JPEG_SOF_RST 8
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#define SOC_USER_ID (MISC_BASE + 0x03C)
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#define RAS_SOF_RST (MISC_BASE + 0x040)
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#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
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#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
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#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
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/* gpt synthesizer register masks */
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#define GPT_MSCALE_SHIFT 0
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#define GPT_MSCALE_MASK 0xFFF
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#define GPT_NSCALE_SHIFT 12
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#define GPT_NSCALE_MASK 0xF
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#define AMEM_CLK_CFG (MISC_BASE + 0x050)
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#define EXPI_CLK_CFG (MISC_BASE + 0x054)
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#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
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#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
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#define UART_CLK_SYNT (MISC_BASE + 0x064)
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#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
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#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
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#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
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#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
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#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
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/* aux clk synthesiser register masks for irda to ras4 */
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#define AUX_SYNT_ENB 31
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#define AUX_EQ_SEL_SHIFT 30
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#define AUX_EQ_SEL_MASK 1
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#define AUX_EQ1_SEL 0
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#define AUX_EQ2_SEL 1
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#define AUX_XSCALE_SHIFT 16
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#define AUX_XSCALE_MASK 0xFFF
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#define AUX_YSCALE_SHIFT 0
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#define AUX_YSCALE_MASK 0xFFF
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#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
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#define ICM2_ARB_CFG (MISC_BASE + 0x080)
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#define ICM3_ARB_CFG (MISC_BASE + 0x084)
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#define ICM4_ARB_CFG (MISC_BASE + 0x088)
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#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
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#define ICM6_ARB_CFG (MISC_BASE + 0x090)
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#define ICM7_ARB_CFG (MISC_BASE + 0x094)
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#define ICM8_ARB_CFG (MISC_BASE + 0x098)
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#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
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#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
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#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
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#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
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#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
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#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
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#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
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#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
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#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
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#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
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#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
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#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
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#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
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#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
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#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
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#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
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#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
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#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
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#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
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#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
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#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
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#define BIST4_CFG_CTR (MISC_BASE + 0x100)
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#define BIST5_CFG_CTR (MISC_BASE + 0x104)
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#define BIST1_STS_RES (MISC_BASE + 0x108)
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#define BIST2_STS_RES (MISC_BASE + 0x10C)
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#define BIST3_STS_RES (MISC_BASE + 0x110)
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#define BIST4_STS_RES (MISC_BASE + 0x114)
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#define BIST5_STS_RES (MISC_BASE + 0x118)
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#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
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#endif /* __MACH_MISC_REGS_H */
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